Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains
ناشر:
سال
: 2014شناسه الکترونیک: 10.1109/TVLSI.2013.2252030
کلیدواژه(گان): clocks,logic design,synchronisation,asynchronous first-input first-output GALS interface,frequency submultiples,globally asynchronous design subset,globally ratiochronous design,locally synchronous design subset,low latency maximal throughput communication interface,rationally related clock domains,rationally related clock frequency,source synchronous adaptive interface,Application specific integrated circuits,asynchronous circuits,circuits,circuits and systems,system-on-a-chip
کالکشن
:
-
آمار بازدید
Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains
Show full item record
| contributor author | Chabloz, Jean-Michel | |
| contributor author | Hemani, Ahmed | |
| date accessioned | 2020-03-12T18:22:56Z | |
| date available | 2020-03-12T18:22:56Z | |
| date issued | 2014 | |
| identifier issn | 1063-8210 | |
| identifier other | 6507330.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/956586 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 7988658 | |
| subject keywords | clocks | |
| subject keywords | logic design | |
| subject keywords | synchronisation | |
| subject keywords | asynchronous first-input first-output GALS interface | |
| subject keywords | frequency submultiples | |
| subject keywords | globally asynchronous design subset | |
| subject keywords | globally ratiochronous design | |
| subject keywords | locally synchronous design subset | |
| subject keywords | low latency maximal throughput communication interface | |
| subject keywords | rationally related clock domains | |
| subject keywords | rationally related clock frequency | |
| subject keywords | source synchronous adaptive interface | |
| subject keywords | Application specific integrated circuits | |
| subject keywords | asynchronous circuits | |
| subject keywords | circuits | |
| subject keywords | circuits and systems | |
| subject keywords | system-on-a-chip | |
| identifier doi | 10.1109/TVLSI.2013.2252030 | |
| journal title | Very Large Scale Integration (VLSI) Systems, IEEE Transactions on | |
| journal volume | 22 | |
| journal issue | 3 | |
| filesize | 762743 | |
| citations | 0 |