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A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning

contributor authorLak, Zahra
contributor authorNicolici, Nicola
date accessioned2020-03-12T18:20:55Z
date available2020-03-12T18:20:55Z
date issued2014
identifier issn0018-9340
identifier other6361380.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/955526?locale-attribute=en&show=full
formatgeneral
languageEnglish
publisherIEEE
titleA Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning
typeJournal Paper
contenttypeMetadata Only
identifier padid7987195
subject keywordsclocks
subject keywordsalgorithmic approach
subject keywordsclock tuning buffers
subject keywordsclock tuning elements
subject keywordsclock vernier devices
subject keywordselectrical effects
subject keywordshigh-performance designs
subject keywordspost-silicon clock tuning
subject keywordspost-silicon delay measurement
subject keywordssmart pruning techniques
subject keywordsAlgorithm design and analysis
subject keywordsClocks
subject keywordsDelay
subject keywordsFrequency measurement
subject keywordsSilicon
subject keywordsTuning
subject keywordsCVD configuration
subject keywordsCVD insertion
subject keywordsClock Vernier Devices (CVDs)
subject keywordsPost-silicon clock tuning
subject keywordsspeedpaths
identifier doi10.1109/TC.2012.275
journal titleComputers, IEEE Transactions on
journal volume63
journal issue5
filesize1512703
citations0


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