A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations
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: 2007DOI: 10.1109/tie.2007.894726
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A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations
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| contributor author | Sridharan, K. | |
| contributor author | Priya, T.K. | |
| date accessioned | 2020-03-11T14:52:47Z | |
| date available | 2020-03-11T14:52:47Z | |
| date issued | 2007 | |
| identifier other | JvoXmEn9jMi4Q7FwF9ZrzjSUb4_okxJ8Zeu776oq2z5JiWIyya.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/566249?locale-attribute=en | |
| format | general | |
| language | English | |
| title | A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations | |
| type | Journal Paper | |
| contenttype | Fulltext | |
| contenttype | Fulltext | |
| identifier padid | 4388125 | |
| identifier doi | 10.1109/tie.2007.894726 | |
| journal title | Osmania Journal of Social Sciences | |
| coverage | Academic | |
| pages | 1800-1804 | |
| journal volume | 54 | |
| journal issue | 3 | |
| filesize | 196083 | |
| citations | 1 |