Proportionally fair flow control mechanism for best effort traffic in network-on-chip architectures

Abstract

The research community has recently witnessed the emergence of multi-processor<br><br>system on chip (MPSoC) platforms consisting of a large set of embedded processors.<br><br>Particularly, Interconnect networks methodology based on network-on-chip (NoC) in<br><br>MPSoC design is imminent to achieve high performance potential. More importantly,<br><br>many well established schemes of networking and distributed systems inspire NoC<br><br>design methodologies. Employing end-to-end congestion control is becoming more<br><br>imminent in the design process of NoCs. This paper presents a centralised congestion<br><br>control scheme in the presence of both elastic and streaming flow traffic mixture. We<br><br>model the desired best effort source rates as the solution to an optimisation problem<br><br>with weighted logarithmic objective which is known to admit proportional fairness<br><br>criterion. The problem is constrained with link capacities while preserving guaranteed<br><br>service traffics services requirements at the desired level. We propose an iterative<br><br>algorithm as the solution to the optimisation problem which has the benefit of low<br><br>complexity and fast convergence, and can be implemented by a controller unit with low<br><br>computation and communication overhead.