A Novel Congestion Control Scheme in Network-on-Chip Based on Best Effort Delay-Sum Optimization
سال
: 2008
چکیده: With the advances of the semiconductor technology,
the enormous number of transistors available on a
single chip allows designers to integrate dozens of IP
blocks together with large amounts of embedded
memory. This has been led to the concept of Network
on a Chip (NoC), in which different modules would be
connected by a simple network of shared links and
routers and is considered as a solution to replace
traditional bus-based architectures to address the
global communication challenges in nanoscale
technologies. In NoC architectures, controlling
congestion of the best effort traffic will continue to be
an important design goal. Towards this, employing
end-to-end congestion control is becoming more
imminent in the design process of NoCs. In this paper,
we introduce a centralized algorithm based on the
delay minimization of Best Effort sources. The
proposed algorithm can be used as a mechanism to
control the flow of Best Effort source rates by which
the sum of propagation delays of network is to be
minimized.
the enormous number of transistors available on a
single chip allows designers to integrate dozens of IP
blocks together with large amounts of embedded
memory. This has been led to the concept of Network
on a Chip (NoC), in which different modules would be
connected by a simple network of shared links and
routers and is considered as a solution to replace
traditional bus-based architectures to address the
global communication challenges in nanoscale
technologies. In NoC architectures, controlling
congestion of the best effort traffic will continue to be
an important design goal. Towards this, employing
end-to-end congestion control is becoming more
imminent in the design process of NoCs. In this paper,
we introduce a centralized algorithm based on the
delay minimization of Best Effort sources. The
proposed algorithm can be used as a mechanism to
control the flow of Best Effort source rates by which
the sum of propagation delays of network is to be
minimized.
کلیدواژه(گان): Network on Chip,Flow Control
کالکشن
:
-
آمار بازدید
A Novel Congestion Control Scheme in Network-on-Chip Based on Best Effort Delay-Sum Optimization
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| contributor author | محمدحسین یغمائی مقدم | en |
| contributor author | Mohammad Hossein Yaghmaee Moghaddam | fa |
| date accessioned | 2020-06-06T13:50:48Z | |
| date available | 2020-06-06T13:50:48Z | |
| date copyright | 5/1/2008 | |
| date issued | 2008 | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/3371631?locale-attribute=fa | |
| description abstract | With the advances of the semiconductor technology, the enormous number of transistors available on a single chip allows designers to integrate dozens of IP blocks together with large amounts of embedded memory. This has been led to the concept of Network on a Chip (NoC), in which different modules would be connected by a simple network of shared links and routers and is considered as a solution to replace traditional bus-based architectures to address the global communication challenges in nanoscale technologies. In NoC architectures, controlling congestion of the best effort traffic will continue to be an important design goal. Towards this, employing end-to-end congestion control is becoming more imminent in the design process of NoCs. In this paper, we introduce a centralized algorithm based on the delay minimization of Best Effort sources. The proposed algorithm can be used as a mechanism to control the flow of Best Effort source rates by which the sum of propagation delays of network is to be minimized. | en |
| language | English | |
| title | A Novel Congestion Control Scheme in Network-on-Chip Based on Best Effort Delay-Sum Optimization | en |
| type | Conference Paper | |
| contenttype | External Fulltext | |
| subject keywords | Network on Chip | en |
| subject keywords | Flow Control | en |
| identifier link | https://profdoc.um.ac.ir/paper-abstract-1006722.html | |
| conference title | International Symposium on Parallel Architectures, Algorithms and Networks | en |
| identifier articleid | 1006722 |