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Post-Layout Simulation Time Reduction for Phase-Locked Loop Frequency Synthesizer Using System Identification Techniques

contributor authorLechang Liu
contributor authorPokharel, R.
date accessioned2020-03-13T00:26:16Z
date available2020-03-13T00:26:16Z
date issued2014
identifier issn0278-0070
identifier other6926919.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1146732?locale-attribute=fa&show=full
formatgeneral
languageEnglish
publisherIEEE
titlePost-Layout Simulation Time Reduction for Phase-Locked Loop Frequency Synthesizer Using System Identification Techniques
typeJournal Paper
contenttypeMetadata Only
identifier padid8329598
subject keywordsautoregressive processes
subject keywordselectronic engineering computing
subject keywordsfrequency synthesizers
subject keywordsphase locked loops
subject keywordsradial basis function networks
subject keywordsPLL frequency synthesizer
subject keywordsautoregressive exogenous model
subject keywordscharge pump
subject keywordscompact model extraction
subject keywordslookup table
subject keywordsloop filter
subject keywordsnonlinear frequency-voltage relationship
subject keywordsnonlinearity compensation
subject keywordsphase-locked loop frequency synthesizer
subject keywordspost-layout simulation time reduction
subject keywordsradial basis function neural network
subject keywordssystem identification technique
subject keywordsvoltage-controlled
identifier doi10.1109/TCAD.2014.2354291
journal titleComputer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
journal volume33
journal issue11
filesize1156388
citations0


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