Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs
Author:
, , , , ,Publisher:
Year
: 2014DOI: 10.1109/TED.2014.2351401
Keyword(s): MOSFET,elemental semiconductors,nanowires,silicon,statistical analysis,titanium compounds,GAA n-NWFET,Si,TiN,coupled 3D statistical device simulations,figure of merit,gate-all-around nanowire n-MOSFET,linear mode,metal-gate crystal grain size,metal-gate granularity-induced threshold voltage variability,quantum corrected room temperature drift-diffusion transport,saturation mode,temperature 293 K to 298 K,FinFETs,Grain size,Logic gates,Nanoscale devices,Silicon,Gate-all-aro
Collections
:
-
Statistics
Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs
Show full item record
| contributor author | Nayak, Kaushik | |
| contributor author | Agarwal, Sankalp | |
| contributor author | Bajaj, Mohit | |
| contributor author | Oldiges, Philip J. | |
| contributor author | Murali, Kota V. R. M. | |
| contributor author | Rao, Valipe Ramgopal | |
| date accessioned | 2020-03-13T00:22:03Z | |
| date available | 2020-03-13T00:22:03Z | |
| date issued | 2014 | |
| identifier issn | 0018-9383 | |
| identifier other | 6895292.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1144063 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8326712 | |
| subject keywords | MOSFET | |
| subject keywords | elemental semiconductors | |
| subject keywords | nanowires | |
| subject keywords | silicon | |
| subject keywords | statistical analysis | |
| subject keywords | titanium compounds | |
| subject keywords | GAA n-NWFET | |
| subject keywords | Si | |
| subject keywords | TiN | |
| subject keywords | coupled 3D statistical device simulations | |
| subject keywords | figure of merit | |
| subject keywords | gate-all-around nanowire n-MOSFET | |
| subject keywords | linear mode | |
| subject keywords | metal-gate crystal grain size | |
| subject keywords | metal-gate granularity-induced threshold voltage variability | |
| subject keywords | quantum corrected room temperature drift-diffusion transport | |
| subject keywords | saturation mode | |
| subject keywords | temperature 293 K to 298 K | |
| subject keywords | FinFETs | |
| subject keywords | Grain size | |
| subject keywords | Logic gates | |
| subject keywords | Nanoscale devices | |
| subject keywords | Silicon | |
| subject keywords | Gate-all-aro | |
| identifier doi | 10.1109/TED.2014.2351401 | |
| journal title | Electron Devices, IEEE Transactions on | |
| journal volume | 61 | |
| journal issue | 11 | |
| filesize | 1314273 | |
| citations | 1 |