A Parallel Radix-Sort-Based VLSI Architecture for Finding the First <inline-formula> <img src="/images/tex/473.gif" alt="W"> </inline-formula> Maximum/Minimum Values
Publisher:
Year
: 2014DOI: 10.1109/TCSII.2014.2350333
Keyword(s): VLSI,codecs,logic circuits,logic design,parallel architectures,parity check codes,turbo codes,BWA architecture,K-best multiple-input-multiple-output detectors,MIMO detectors,area-delay product,bit-wise-and architecture,high-speed CMOS standard-cell technology,maximum/minimum values,nonbinary low-density-parity-check decoders,parallel radix-sort-based VLSI architecture,size 90 nm,turbo product codes,very simple logic circuits,very-large-scale integration architectures,Computer
Collections
:
-
Statistics
A Parallel Radix-Sort-Based VLSI Architecture for Finding the First <inline-formula> <img src="/images/tex/473.gif" alt="W"> </inline-formula> Maximum/Minimum Values
Show full item record
| contributor author | Guoping Xiao | |
| contributor author | Martina, Maurizio | |
| contributor author | Masera, Guido | |
| contributor author | Piccinini, G. | |
| date accessioned | 2020-03-13T00:19:32Z | |
| date available | 2020-03-13T00:19:32Z | |
| date issued | 2014 | |
| identifier issn | 1549-7747 | |
| identifier other | 6881635.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1142558?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A Parallel Radix-Sort-Based VLSI Architecture for Finding the First <inline-formula> <img src="/images/tex/473.gif" alt="W"> </inline-formula> Maximum/Minimum Values | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8325101 | |
| subject keywords | VLSI | |
| subject keywords | codecs | |
| subject keywords | logic circuits | |
| subject keywords | logic design | |
| subject keywords | parallel architectures | |
| subject keywords | parity check codes | |
| subject keywords | turbo codes | |
| subject keywords | BWA architecture | |
| subject keywords | K-best multiple-input-multiple-output detectors | |
| subject keywords | MIMO detectors | |
| subject keywords | area-delay product | |
| subject keywords | bit-wise-and architecture | |
| subject keywords | high-speed CMOS standard-cell technology | |
| subject keywords | maximum/minimum values | |
| subject keywords | nonbinary low-density-parity-check decoders | |
| subject keywords | parallel radix-sort-based VLSI architecture | |
| subject keywords | size 90 nm | |
| subject keywords | turbo product codes | |
| subject keywords | very simple logic circuits | |
| subject keywords | very-large-scale integration architectures | |
| subject keywords | Computer | |
| identifier doi | 10.1109/TCSII.2014.2350333 | |
| journal title | Circuits and Systems II: Express Briefs, IEEE Transactions on | |
| journal volume | 61 | |
| journal issue | 11 | |
| filesize | 543599 | |
| citations | 0 |