A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology
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Year
: 2014DOI: 10.1109/JSSC.2014.2340574
Keyword(s): CMOS integrated circuits,clock and data recovery circuits,error statistics,feedforward,integrated circuit design,jitter,low-power electronics,silicon-on-insulator,transceivers,CDR,DFE transceiver,FFE,FFR scheme,SOI CMOS technology,Si,backplane transceiver,bit rate 32 Gbit/s,bit-error rate,clock and data recovery,decision feedback,feed-forward equalization,high-frequency jitter tolerance,on-chip AC-coupling network,passive feed-forward restore scheme,pattern-dependent base
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A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology
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| contributor author | Gangasani, Gautam R. | |
| contributor author | Chun-Ming Hsu | |
| contributor author | Bulzacchelli, John F. | |
| contributor author | Beukema, Troy | |
| contributor author | Kelly, Wayne | |
| contributor author | Xu, Hui H. | |
| contributor author | Freitas, David | |
| contributor author | Prati, Andrea | |
| contributor author | Gardellini, Daniele | |
| contributor author | Reutemann, Robert | |
| contributor author | Cervelli, Giovanni | |
| contributor author | Hertle, Juergen | |
| contributor author | Baecher, Matthew | |
| contributor author | Garlett, Jon | |
| contributor author | Francese, Pier-Andrea | |
| contributor author | Ewen, John F. | |
| contributor author | Hanson, D. | |
| contributor author | Storaska, Daniel W. | |
| contributor author | Meghelli, Mounir | |
| date accessioned | 2020-03-13T00:17:17Z | |
| date available | 2020-03-13T00:17:17Z | |
| date issued | 2014 | |
| identifier issn | 0018-9200 | |
| identifier other | 6872604.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1141172?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8323601 | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | clock and data recovery circuits | |
| subject keywords | error statistics | |
| subject keywords | feedforward | |
| subject keywords | integrated circuit design | |
| subject keywords | jitter | |
| subject keywords | low-power electronics | |
| subject keywords | silicon-on-insulator | |
| subject keywords | transceivers | |
| subject keywords | CDR | |
| subject keywords | DFE transceiver | |
| subject keywords | FFE | |
| subject keywords | FFR scheme | |
| subject keywords | SOI CMOS technology | |
| subject keywords | Si | |
| subject keywords | backplane transceiver | |
| subject keywords | bit rate 32 Gbit/s | |
| subject keywords | bit-error rate | |
| subject keywords | clock and data recovery | |
| subject keywords | decision feedback | |
| subject keywords | feed-forward equalization | |
| subject keywords | high-frequency jitter tolerance | |
| subject keywords | on-chip AC-coupling network | |
| subject keywords | passive feed-forward restore scheme | |
| subject keywords | pattern-dependent base | |
| identifier doi | 10.1109/JSSC.2014.2340574 | |
| journal title | Solid-State Circuits, IEEE Journal of | |
| journal volume | 49 | |
| journal issue | 11 | |
| filesize | 4058521 | |
| citations | 1 |