A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios
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: 2014DOI: 10.1109/JSSC.2014.2334392
Keyword(s): calibration,frequency dividers,frequency synthesizers,phase locked loops,phase noise,software radio,CMOS process,ILFD,PLL,PVT variation,SDR,digital calibration scheme,frequency 10 MHz to 6.6 GHz,injection-locked frequency divider,injection-locking operation,low-power fractionally injection-locked quadrature frequency synthesizer,normalized phase noise,phase-locked loop,power 16 mW to 26 mW,process voltage and temperature variation,quadrature phase output,self-synchronized ga
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A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios
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| contributor author | Wei Deng | |
| contributor author | Hara, S. | |
| contributor author | Musa, A. | |
| contributor author | Okada, K. | |
| contributor author | Matsuzawa, A. | |
| date accessioned | 2020-03-13T00:14:56Z | |
| date available | 2020-03-13T00:14:56Z | |
| date issued | 2014 | |
| identifier issn | 0018-9200 | |
| identifier other | 6862065.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1139733?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8321991 | |
| subject keywords | calibration | |
| subject keywords | frequency dividers | |
| subject keywords | frequency synthesizers | |
| subject keywords | phase locked loops | |
| subject keywords | phase noise | |
| subject keywords | software radio | |
| subject keywords | CMOS process | |
| subject keywords | ILFD | |
| subject keywords | PLL | |
| subject keywords | PVT variation | |
| subject keywords | SDR | |
| subject keywords | digital calibration scheme | |
| subject keywords | frequency 10 MHz to 6.6 GHz | |
| subject keywords | injection-locked frequency divider | |
| subject keywords | injection-locking operation | |
| subject keywords | low-power fractionally injection-locked quadrature frequency synthesizer | |
| subject keywords | normalized phase noise | |
| subject keywords | phase-locked loop | |
| subject keywords | power 16 mW to 26 mW | |
| subject keywords | process voltage and temperature variation | |
| subject keywords | quadrature phase output | |
| subject keywords | self-synchronized ga | |
| identifier doi | 10.1109/JSSC.2014.2334392 | |
| journal title | Solid-State Circuits, IEEE Journal of | |
| journal volume | 49 | |
| journal issue | 9 | |
| filesize | 2125062 | |
| citations | 0 |