A Low Energy and High Performance <formula formulatype="inline"> <img src="/images/tex/21488.gif" alt="{\\rm DM}^{2}"> </formula> Adder
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Year
: 2014DOI: 10.1109/TCSI.2014.2334793
Keyword(s): adders,logic design,low-power electronics,probabilistic logic,dual mode square adder,dual-mode addition,dual-mode logic,gate topology,high performance DM<,sup>,2<,/sup>,adder,multicycle operation,pipelined processor,probability based circuit architecture,real time system requirements,size 40 nm,wide energy-performance tradeoff,word length 32 bit,word length 64 bit,Adders,CMOS integrated circuits,Clocks,Delays,Logic gates,Topology,Transistors,Adders,DML,low-powe
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A Low Energy and High Performance <formula formulatype="inline"> <img src="/images/tex/21488.gif" alt="{\\rm DM}^{2}"> </formula> Adder
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| contributor author | Levi, Itamar | |
| contributor author | Albeck, Amir | |
| contributor author | Fish, Alexander | |
| contributor author | Wimer, Shmuel | |
| date accessioned | 2020-03-13T00:14:25Z | |
| date available | 2020-03-13T00:14:25Z | |
| date issued | 2014 | |
| identifier issn | 1549-8328 | |
| identifier other | 6858090.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1139384 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A Low Energy and High Performance <formula formulatype="inline"> <img src="/images/tex/21488.gif" alt="{\\rm DM}^{2}"> </formula> Adder | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8321603 | |
| subject keywords | adders | |
| subject keywords | logic design | |
| subject keywords | low-power electronics | |
| subject keywords | probabilistic logic | |
| subject keywords | dual mode square adder | |
| subject keywords | dual-mode addition | |
| subject keywords | dual-mode logic | |
| subject keywords | gate topology | |
| subject keywords | high performance DM< | |
| subject keywords | sup> | |
| subject keywords | 2< | |
| subject keywords | /sup> | |
| subject keywords | adder | |
| subject keywords | multicycle operation | |
| subject keywords | pipelined processor | |
| subject keywords | probability based circuit architecture | |
| subject keywords | real time system requirements | |
| subject keywords | size 40 nm | |
| subject keywords | wide energy-performance tradeoff | |
| subject keywords | word length 32 bit | |
| subject keywords | word length 64 bit | |
| subject keywords | Adders | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | Clocks | |
| subject keywords | Delays | |
| subject keywords | Logic gates | |
| subject keywords | Topology | |
| subject keywords | Transistors | |
| subject keywords | Adders | |
| subject keywords | DML | |
| subject keywords | low-powe | |
| identifier doi | 10.1109/TCSI.2014.2334793 | |
| journal title | Circuits and Systems I: Regular Papers, IEEE Transactions on | |
| journal volume | 61 | |
| journal issue | 11 | |
| filesize | 1965358 | |
| citations | 0 |