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Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time

contributor authorNissimoff, Albert
contributor authorMartino, Joao Antonio
contributor authorAoulaiche, Marc
contributor authorVeloso, A.
contributor authorWitters, Liesbeth Johanna
contributor authorSimoen, Eddy
contributor authorClaeys, Cor
date accessioned2020-03-13T00:02:25Z
date available2020-03-13T00:02:25Z
date issued2014
identifier issn0741-3106
identifier other6811203.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1132227?locale-attribute=en&show=full
formatgeneral
languageEnglish
publisherIEEE
titleSpike Anneal Peak Temperature Impact on 1T-DRAM Retention Time
typeJournal Paper
contenttypeMetadata Only
identifier padid8313173
subject keywordsDRAM chips
subject keywordsannealing
subject keywordssilicon-on-insulator
subject keywords1T-DRAM retention time
subject keywordsSOI
subject keywordsdrain electrical field
subject keywordsdrain implantation
subject keywordsdynamic random access memory cells
subject keywordssingle silicon-on-insulator transistor
subject keywordssource implantation
subject keywordsspike anneal peak temperature
subject keywordstemperature 1070 degC to 1050 degC
subject keywordstemperature 20 degC
subject keywordstunneling current
subject keywordsAnnealing
subject keywordsLogic gates
subject keywordsMathematical model
subject keywordsRandom access memory
subject keywordsTime measurement
subject keywordsTransistors
subject keywordsTunneling
subject keywords1T-DRAM
subject keywords1T-DRAM.
subject keywordsCapacitorless DRAM
subject keywordsSOI
identifier doi10.1109/LED.2014.2319094
journal titleElectron Device Letters, IEEE
journal volume35
journal issue6
filesize703462
citations0


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