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A Novel Quasi-3-D Interface-Trapped-Charge-Induced Threshold Voltage Model for Quadruple-Gate MOSFETs, Including Equivalent Number of Gates

contributor authorChiang Te-Kuang
date accessioned2020-03-12T23:55:55Z
date available2020-03-12T23:55:55Z
date issued2014
identifier issn0018-9383
identifier other6782652.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1128481?locale-attribute=en&show=full
formatgeneral
languageEnglish
publisherIEEE
titleA Novel Quasi-3-D Interface-Trapped-Charge-Induced Threshold Voltage Model for Quadruple-Gate MOSFETs, Including Equivalent Number of Gates
typeJournal Paper
contenttypeMetadata Only
identifier padid8308652
subject keywordsMOSFET
subject keywordselemental semiconductors
subject keywordsinterface states
subject keywordssemiconductor device models
subject keywordssilicon
subject keywordsSi
subject keywordshot-carrier-induced threshold voltage
subject keywordsmemory device
subject keywordsnegative trapped charges
subject keywordsquadruple-gate MOSFET
subject keywordsquasi-3-D interface-trapped-charge-induced threshold voltage model
subject keywordsthin gate oxide
subject keywordsthreshold voltage degradation
subject keywordsLogic gates
subject keywordsMOSFET
subject keywordsMathematical model
subject keywordsSemiconductor device modeling
subject keywordsSilicon
subject keywordsThreshold voltage
subject keywordsBulk scaling equation
subject keywordsequivalent number of gates (ENG)
subject keywordsinterface-trapped-charge-induc
identifier doi10.1109/TED.2014.2312922
journal titleElectron Devices, IEEE Transactions on
journal volume61
journal issue5
filesize973665
citations0


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