A Novel Quasi-3-D Interface-Trapped-Charge-Induced Threshold Voltage Model for Quadruple-Gate MOSFETs, Including Equivalent Number of Gates
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: 2014DOI: 10.1109/TED.2014.2312922
Keyword(s): MOSFET,elemental semiconductors,interface states,semiconductor device models,silicon,Si,hot-carrier-induced threshold voltage,memory device,negative trapped charges,quadruple-gate MOSFET,quasi-3-D interface-trapped-charge-induced threshold voltage model,thin gate oxide,threshold voltage degradation,Logic gates,MOSFET,Mathematical model,Semiconductor device modeling,Silicon,Threshold voltage,Bulk scaling equation,equivalent number of gates (ENG),interface-trapped-charge-induc
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A Novel Quasi-3-D Interface-Trapped-Charge-Induced Threshold Voltage Model for Quadruple-Gate MOSFETs, Including Equivalent Number of Gates
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| contributor author | Chiang Te-Kuang | |
| date accessioned | 2020-03-12T23:55:55Z | |
| date available | 2020-03-12T23:55:55Z | |
| date issued | 2014 | |
| identifier issn | 0018-9383 | |
| identifier other | 6782652.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1128481?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A Novel Quasi-3-D Interface-Trapped-Charge-Induced Threshold Voltage Model for Quadruple-Gate MOSFETs, Including Equivalent Number of Gates | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8308652 | |
| subject keywords | MOSFET | |
| subject keywords | elemental semiconductors | |
| subject keywords | interface states | |
| subject keywords | semiconductor device models | |
| subject keywords | silicon | |
| subject keywords | Si | |
| subject keywords | hot-carrier-induced threshold voltage | |
| subject keywords | memory device | |
| subject keywords | negative trapped charges | |
| subject keywords | quadruple-gate MOSFET | |
| subject keywords | quasi-3-D interface-trapped-charge-induced threshold voltage model | |
| subject keywords | thin gate oxide | |
| subject keywords | threshold voltage degradation | |
| subject keywords | Logic gates | |
| subject keywords | MOSFET | |
| subject keywords | Mathematical model | |
| subject keywords | Semiconductor device modeling | |
| subject keywords | Silicon | |
| subject keywords | Threshold voltage | |
| subject keywords | Bulk scaling equation | |
| subject keywords | equivalent number of gates (ENG) | |
| subject keywords | interface-trapped-charge-induc | |
| identifier doi | 10.1109/TED.2014.2312922 | |
| journal title | Electron Devices, IEEE Transactions on | |
| journal volume | 61 | |
| journal issue | 5 | |
| filesize | 973665 | |
| citations | 0 |