A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices
Publisher:
Year
: 2014DOI: 10.1109/LES.2014.2311317
Keyword(s): graphics processing units,parity check codes,BER,GPU devices,LDPC code performance estimation,LDPC decoding process,bit error rate,computation parallelism,correction performance,decoder iteration,digital communication applications,flooding-based decoding algorithm,graphics processing unit,high throughput efficient approach,layered schedules,low density parity check codes,memory access patterns,Decoding,Graphics processing units,Iterative decoding,Kernel,Performance evaluatio
Collections
:
-
Statistics
A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices
Show full item record
| contributor author | Le Gal, Bertrand | |
| contributor author | Jego, Christophe | |
| contributor author | Crenne, Jeremie | |
| date accessioned | 2020-03-12T23:51:10Z | |
| date available | 2020-03-12T23:51:10Z | |
| date issued | 2014 | |
| identifier issn | 1943-0663 | |
| identifier other | 6762823.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1125663?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8305344 | |
| subject keywords | graphics processing units | |
| subject keywords | parity check codes | |
| subject keywords | BER | |
| subject keywords | GPU devices | |
| subject keywords | LDPC code performance estimation | |
| subject keywords | LDPC decoding process | |
| subject keywords | bit error rate | |
| subject keywords | computation parallelism | |
| subject keywords | correction performance | |
| subject keywords | decoder iteration | |
| subject keywords | digital communication applications | |
| subject keywords | flooding-based decoding algorithm | |
| subject keywords | graphics processing unit | |
| subject keywords | high throughput efficient approach | |
| subject keywords | layered schedules | |
| subject keywords | low density parity check codes | |
| subject keywords | memory access patterns | |
| subject keywords | Decoding | |
| subject keywords | Graphics processing units | |
| subject keywords | Iterative decoding | |
| subject keywords | Kernel | |
| subject keywords | Performance evaluatio | |
| identifier doi | 10.1109/LES.2014.2311317 | |
| journal title | Embedded Systems Letters, IEEE | |
| journal volume | 6 | |
| journal issue | 2 | |
| filesize | 615123 | |
| citations | 0 |