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Application specific optimization of coarse-grained reconfigurable architecture by dynamic context compression

contributor authorPriyadharsini, S.
contributor authorSrilalitha, A.
date accessioned2020-03-12T23:00:00Z
date available2020-03-12T23:00:00Z
date issued2014
identifier other7033779.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1101994?locale-attribute=fa&show=full
formatgeneral
languageEnglish
publisherIEEE
titleApplication specific optimization of coarse-grained reconfigurable architecture by dynamic context compression
typeConference Paper
contenttypeMetadata Only
identifier padid8244499
subject keywordsEducational institutions
subject keywordsn Heterojunction bipolar transistors
subject keywordsn Inverters
subject keywordsn Switches
subject keywordsn Torque control
subject keywordsn Vectors
subject keywordsn Diode clamped inverter
subject keywordsn Direct torque control
subject keywordsn Induction Motor
subject keywordsn Multilevel inverter
subject keywordsn ST-DTC
subject keywordsn Three level Inverter
identifier doi10.1109/ICCPEIC.2014.6915366
journal titlenformation Communication and Embedded Systems (ICICES), 2014 International Conference on
filesize767306
citations0


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