A +33dBm 1.9 GHz linear CMOS power amplifier with MOS-level linearizers
| contributor author | Ren, Zhixiong | |
| contributor author | Zhang, Kefeng | |
| contributor author | Liu, Lanqi | |
| contributor author | Li, Cong | |
| contributor author | Chen, Xiaofei | |
| contributor author | Liu, Dongsheng | |
| contributor author | Liu, Zhenglin | |
| contributor author | Zou, Xuecheng | |
| date accessioned | 2020-03-12T22:54:56Z | |
| date available | 2020-03-12T22:54:56Z | |
| date issued | 2014 | |
| identifier other | 7029494.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1099006?locale-attribute=fa&show=full | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A +33dBm 1.9 GHz linear CMOS power amplifier with MOS-level linearizers | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8240462 | |
| identifier doi | 10.1109/AGILE.2014.19 | |
| journal title | ntegrated Circuits (ISIC), 2014 14th International Symposium on | |
| filesize | 162635 | |
| citations | 0 |
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