A Personalized Geographic-Based Diffusion Model for Location Recommendations in LBSN
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Year
: 2014DOI: 10.1109/IPDPS.2014.39
Keyword(s): fault tolerant computing,n integrated circuit design,n integrated circuit reliability,n multiprocessing systems,n network routing,n network-on-chip,n Bullet Proof,n Cadence encounter RTL compiler,n GEM5,n MTTF,n PARSEC benchmark application traffic,n RoCo,n SPF analysis,n SPLASH-2,n Vicis,n aggressive technology scaling,n area overhead,n correction circuitry,n deep nanometer regime,n fault-tolerant routers,n hardware synthesis,n impr
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A Personalized Geographic-Based Diffusion Model for Location Recommendations in LBSN
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| contributor author | Nunes, Iury | |
| contributor author | Marinho, Leandro | |
| date accessioned | 2020-03-12T22:16:05Z | |
| date available | 2020-03-12T22:16:05Z | |
| date issued | 2014 | |
| identifier other | 7000172.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1077059?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A Personalized Geographic-Based Diffusion Model for Location Recommendations in LBSN | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8213296 | |
| subject keywords | fault tolerant computing | |
| subject keywords | n integrated circuit design | |
| subject keywords | n integrated circuit reliability | |
| subject keywords | n multiprocessing systems | |
| subject keywords | n network routing | |
| subject keywords | n network-on-chip | |
| subject keywords | n Bullet Proof | |
| subject keywords | n Cadence encounter RTL compiler | |
| subject keywords | n GEM5 | |
| subject keywords | n MTTF | |
| subject keywords | n PARSEC benchmark application traffic | |
| subject keywords | n RoCo | |
| subject keywords | n SPF analysis | |
| subject keywords | n SPLASH-2 | |
| subject keywords | n Vicis | |
| subject keywords | n aggressive technology scaling | |
| subject keywords | n area overhead | |
| subject keywords | n correction circuitry | |
| subject keywords | n deep nanometer regime | |
| subject keywords | n fault-tolerant routers | |
| subject keywords | n hardware synthesis | |
| subject keywords | n impr | |
| identifier doi | 10.1109/IPDPS.2014.39 | |
| journal title | eb Congress (LA-WEB), 2014 9th Latin American | |
| filesize | 689236 | |
| citations | 0 |