Quiet Area Detection in 3D Sound Field Simulation via Delaunay Triangulation
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Year
: 2014DOI: 10.1109/IOLTS.2014.6873682
Keyword(s): BCH codes,n decoding,n error correction codes,n error detection codes,n storage management chips,n 1-bit errors,n 3-bit errors,n DEC-TED BCH code,n Hsiao SEC-DED codes,n adjacent 2-bit errors,n adjacent errors,n area consumption,n bit positions,n check bits,n data per memory cell,n decoding latency,n double error correcting codes,n modified DEC BCH codes,n multilevel memories,n parallel correction,n storage capacity 8 bit to 1024 bit
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Quiet Area Detection in 3D Sound Field Simulation via Delaunay Triangulation
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| contributor author | Liang, Xiaoyan | |
| contributor author | Fan, Zhe | |
| contributor author | Lin, Ge | |
| contributor author | Luo, Xiaonan | |
| date accessioned | 2020-03-12T22:10:54Z | |
| date available | 2020-03-12T22:10:54Z | |
| date issued | 2014 | |
| identifier other | 6996795.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1074221?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Quiet Area Detection in 3D Sound Field Simulation via Delaunay Triangulation | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8210356 | |
| subject keywords | BCH codes | |
| subject keywords | n decoding | |
| subject keywords | n error correction codes | |
| subject keywords | n error detection codes | |
| subject keywords | n storage management chips | |
| subject keywords | n 1-bit errors | |
| subject keywords | n 3-bit errors | |
| subject keywords | n DEC-TED BCH code | |
| subject keywords | n Hsiao SEC-DED codes | |
| subject keywords | n adjacent 2-bit errors | |
| subject keywords | n adjacent errors | |
| subject keywords | n area consumption | |
| subject keywords | n bit positions | |
| subject keywords | n check bits | |
| subject keywords | n data per memory cell | |
| subject keywords | n decoding latency | |
| subject keywords | n double error correcting codes | |
| subject keywords | n modified DEC BCH codes | |
| subject keywords | n multilevel memories | |
| subject keywords | n parallel correction | |
| subject keywords | n storage capacity 8 bit to 1024 bit | |
| identifier doi | 10.1109/IOLTS.2014.6873682 | |
| journal title | igital Home (ICDH), 2014 5th International Conference on | |
| filesize | 2413178 | |
| citations | 0 |