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Design and verification of five port router for network on chip

contributor authorChoudhari, E.M.
contributor authorDakhole, P.K.
date accessioned2020-03-12T21:37:00Z
date available2020-03-12T21:37:00Z
date issued2014
identifier other6949913.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1054647?locale-attribute=en&show=full
formatgeneral
languageEnglish
publisherIEEE
titleDesign and verification of five port router for network on chip
typeConference Paper
contenttypeMetadata Only
identifier padid8185291
subject keywordsclocks
subject keywordsn computational complexity
subject keywordsn integrated circuit design
subject keywordsn integrated circuit interconnections
subject keywordsn integrated circuit modelling
subject keywordsn network-on-chip
subject keywordsn CDC cost
subject keywordsn CDCs
subject keywordsn NP-hard problem
subject keywordsn NoC architectures
subject keywordsn NoC topology generation
subject keywordsn SoC designs
subject keywordsn automated topology generation tools
subject keywordsn clock domain minimization
subject keywordsn clock-domain-crossings
subject keywordsn communication constraints
subject keywordsn interconnection architecture
subject keywordsn network on chip interconnect
subject keywordsn regular topology
identifier doi10.1109/ISQED.2014.6783339
journal titleommunications and Signal Processing (ICCSP), 2014 International Conference on
filesize1785147
citations0


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