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A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS

contributor authorHiienkari, M.
contributor authorTeittinen, J.
contributor authorKoskinen, L.
contributor authorTurnquist, M.
contributor authorKaltiokallio, M.
date accessioned2020-03-12T21:31:43Z
date available2020-03-12T21:31:43Z
date issued2014
identifier other6946095.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1051726?locale-attribute=fa&show=full
formatgeneral
languageEnglish
publisherIEEE
titleA 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS
typeConference Paper
contenttypeMetadata Only
identifier padid8181818
subject keywordsbiomedical electronics
subject keywordsn flexible electronics
subject keywordsn magnetic resonance
subject keywordsn organic field effect transistors
subject keywordsn radiofrequency power transmission
subject keywordsn sensors
subject keywordsn FWSS
subject keywordsn biomedical applications
subject keywordsn blood detection
subject keywordsn constant monitoring
subject keywordsn data transmission
subject keywordsn elderly-care applications
subject keywordsn frequency 13.56 MHz
subject keywordsn low-cost device
subject keywordsn magnetic resonance
subject keywordsn nursing-care
subject keywordsn organic-transistor-based ESD-tolerant flexible wet sensor sheet
subject keywordsn rigid wet sensor
subject keywordsn urination dete
identifier doi10.1109/ISSCC.2014.6757525
journal titleustom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
filesize751743
citations0


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