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A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN

contributor authorKundu, S.
contributor authorLu, J.H.
contributor authorAlpman, E.
contributor authorLakdawala, H.
contributor authorParamesh, J.
contributor authorByunghoo Jung
contributor authorZur, S.
contributor authorGordon, E.
date accessioned2020-03-12T21:31:32Z
date available2020-03-12T21:31:32Z
date issued2014
identifier other6945992.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1051620?locale-attribute=en&show=full
formatgeneral
languageEnglish
publisherIEEE
titleA 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN
typeConference Paper
contenttypeMetadata Only
identifier padid8181685
subject keywordsMOSFET
subject keywordsn differential amplifiers
subject keywordsn intermodulation distortion
subject keywordsn millimetre wave power amplifiers
subject keywordsn 16-QAM
subject keywordsn 64-QAM
subject keywordsn ACPR
subject keywordsn AM-PM distortion
subject keywordsn Class-AB PA
subject keywordsn Class-AB biasing
subject keywordsn Class-B PA
subject keywordsn Class-B biasing
subject keywordsn EVM
subject keywordsn IEEE 802.11ad
subject keywordsn IEEE 802.15.3c
subject keywordsn NMOS PMOS transistors
subject keywordsn OFDM mode
subject keywordsn OFDM systems
subject keywordsn PAPR
subject keywordsn amplitude-to-phase-modulation distortion
subject keywordsn complementary push-pull PA
subject keywordsn high-fidelity amplification
subject keywordsn high-order modulation scheme
identifier doi10.1109/ISSCC.2014.6757422
journal titleustom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the
filesize371257
citations0


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