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Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm

contributor authorLeyva, P.
contributor authorDomenech-Asensi, G.
contributor authorGarrigos, J.
contributor authorIllade-Quinteiro, J.
contributor authorBrea, V.M.
contributor authorLopez, P.
contributor authorCabello, D.
date accessioned2020-03-12T21:09:33Z
date available2020-03-12T21:09:33Z
date issued2014
identifier other6927409.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1039032?locale-attribute=fa&show=full
formatgeneral
languageEnglish
publisherIEEE
titleSimplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm
typeConference Paper
contenttypeMetadata Only
identifier padid8165774
subject keywordsMRAM devices
subject keywordsreliability
subject keywordsCMOS integration capability
subject keywordsSTT-MRAM
subject keywordsaging phenomena
subject keywordsblock level granularity
subject keywordserror correction
subject keywordsmagnetic random access memory
subject keywordsprocess variability
subject keywordsreliability estimation
subject keywordsspin transfer torque MRAM
subject keywordsDiscrete Fourier transforms
subject keywordsError correction codes
subject keywordsFault tolerance
subject keywordsFault tolerant systems
subject keywordsNanotechnology
subject keywordsVery large scale integration
subject keywordsEmerging memories
subject keywordsMemory Reliability
subject keywordsSTT-MRAM
identifier doi10.1109/DFT.2014.6962093
journal titleield Programmable Logic and Applications (FPL), 2014 24th International Conference on
filesize419838
citations0


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