FPGA implementation of low-power split-radix FFT processors
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Year
: 2014DOI: 10.1109/ISEMC.2014.6898946
Keyword(s): Capacitance,Integrated circuit modeling,Jitter,Noise,Switches,Switching frequency,System-on-chip,jitter,on-chip voltage regulator module (VRM),power distribution network,power/ground noise
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FPGA implementation of low-power split-radix FFT processors
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| contributor author | Zhuo Qian | |
| contributor author | Nasiri, N. | |
| contributor author | Segal, O. | |
| contributor author | Margala, M. | |
| date accessioned | 2020-03-12T21:09:29Z | |
| date available | 2020-03-12T21:09:29Z | |
| date issued | 2014 | |
| identifier other | 6927379.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1039001?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | FPGA implementation of low-power split-radix FFT processors | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8165736 | |
| subject keywords | Capacitance | |
| subject keywords | Integrated circuit modeling | |
| subject keywords | Jitter | |
| subject keywords | Noise | |
| subject keywords | Switches | |
| subject keywords | Switching frequency | |
| subject keywords | System-on-chip | |
| subject keywords | jitter | |
| subject keywords | on-chip voltage regulator module (VRM) | |
| subject keywords | power distribution network | |
| subject keywords | power/ground noise | |
| identifier doi | 10.1109/ISEMC.2014.6898946 | |
| journal title | ield Programmable Logic and Applications (FPL), 2014 24th International Conference on | |
| filesize | 179070 | |
| citations | 0 |