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Low latency book handling in FPGA for high frequency trading

contributor authorDvorak, Milan , Korenek, Jan
date accessioned2020-03-12T20:24:54Z
date available2020-03-12T20:24:54Z
date issued2014
identifier other6868785.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/1013676?locale-attribute=en&show=full
formatgeneral
languageEnglish
publisherIEEE
titleLow latency book handling in FPGA for high frequency trading
typeConference Paper
contenttypeMetadata Only
identifier padid8136811
subject keywordsHardware
subject keywordsOptimization
subject keywordsQuality of service
subject keywordsSwitches
subject keywordsTelecommunication network reliability
subject keywordsData center
subject keywordsHypervisor
subject keywordsNFV
subject keywordsSDN
subject keywordsVM
subject keywordscloud computing
identifier doi10.1109/ICACCI.2014.6968453
journal titleesign and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on
filesize107015
citations1


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