Area-efficient capacitor-less LDR with enhanced transient response for SoC in 65-nm CMOS
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: 2014DOI: 10.1109/SMC.2014.6974127
Keyword(s): Computer aided software engineering,Prototypes,Adaptive shared controls,Brain computer interface (BCI),EEG
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Area-efficient capacitor-less LDR with enhanced transient response for SoC in 65-nm CMOS
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| contributor author | Fan Yang , Mok, P.K.T. | |
| date accessioned | 2020-03-12T20:21:52Z | |
| date available | 2020-03-12T20:21:52Z | |
| date issued | 2014 | |
| identifier other | 6865637.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1011802?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Area-efficient capacitor-less LDR with enhanced transient response for SoC in 65-nm CMOS | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8134429 | |
| subject keywords | Computer aided software engineering | |
| subject keywords | Prototypes | |
| subject keywords | Adaptive shared controls | |
| subject keywords | Brain computer interface (BCI) | |
| subject keywords | EEG | |
| identifier doi | 10.1109/SMC.2014.6974127 | |
| journal title | ircuits and Systems (ISCAS), 2014 IEEE International Symposium on | |
| filesize | 879338 | |
| citations | 1 |