Considering variation and aging in a full chip design methodology at system level
| date accessioned | 2020-03-12T20:05:05Z | |
| date available | 2020-03-12T20:05:05Z | |
| date issued | 2014 | |
| identifier other | 6850386.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1001183?locale-attribute=en&show=full | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Considering variation and aging in a full chip design methodology at system level | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8122046 | |
| subject keywords | Computer architecture | |
| subject keywords | Computers | |
| subject keywords | Data transfer | |
| subject keywords | Field programmable gate arrays | |
| subject keywords | Radar imaging | |
| subject keywords | FMCW | |
| subject keywords | FPGA | |
| subject keywords | Radar | |
| subject keywords | SuperSpeed | |
| subject keywords | USB-3.0 | |
| identifier doi | 10.1109/ReConFig.2014.7032498 | |
| journal title | lectronic System Level Synthesis Conference (ESLsyn), Proceedings of the 2014 | |
| filesize | 237888 | |
| citations | 0 | |
| contributor rawauthor | Helms, D. , Gruttner, K. , Eilers, R. , Metzdorf, M. , Hylla, K. , Poppen, F. , Nebel, W. |
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