Session 2: Work-in-progress
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Year
: 2014DOI: 10.1109/ReConFig.2014.7032492
Keyword(s): Algorithm design and analysis,Computer architecture,Convolution,Detectors,Feature extraction,Hardware,Registers,FPGA,Feature extraction,SURF,reconfigurable computing,rotation-invariant,scale-invariant
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Session 2: Work-in-progress
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| date accessioned | 2020-03-12T20:05:04Z | |
| date available | 2020-03-12T20:05:04Z | |
| date issued | 2014 | |
| identifier other | 6850380.pdf | |
| identifier uri | https://libsearch.um.ac.ir:443/fum/handle/fum/1001177?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Session 2: Work-in-progress | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8122040 | |
| subject keywords | Algorithm design and analysis | |
| subject keywords | Computer architecture | |
| subject keywords | Convolution | |
| subject keywords | Detectors | |
| subject keywords | Feature extraction | |
| subject keywords | Hardware | |
| subject keywords | Registers | |
| subject keywords | FPGA | |
| subject keywords | Feature extraction | |
| subject keywords | SURF | |
| subject keywords | reconfigurable computing | |
| subject keywords | rotation-invariant | |
| subject keywords | scale-invariant | |
| identifier doi | 10.1109/ReConFig.2014.7032492 | |
| journal title | lectronic System Level Synthesis Conference (ESLsyn), Proceedings of the 2014 | |
| filesize | 81756 | |
| citations | 0 |