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نمایش تعداد 1-6 از 6

Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding

نوع: Journal Paper

نویسنده : Condo, Carlo; Baghdadi, Amer; Masera, Guido

ناشر: IET

سال: 2014

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

نوع: Journal Paper

نویسنده : Martina, Maurizio; Papaharalabos, Stylianos; Mathiopoulos, P. Takis; Masera, Guido

ناشر: IEEE

سال: 2014

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First <inline-formula> <img src="/images/tex/473.gif" alt="W"> </inline-formula> Maximum/Minimum Values

نوع: Journal Paper

نویسنده : Guoping Xiao; Martina, Maurizio; Masera, Guido; Piccinini, G.

ناشر: IEEE

سال: 2014

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors

نوع: Journal Paper

نویسنده : Martina, Maurizio; Condo, Carlo; Masera, Guido; Zamboni, Maurizio

ناشر: IEEE

سال: 2014

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation

نوع: Journal Paper

نویسنده : Awais, Muhammad; Masera, Guido; Martina, Maurizio; Montorsi, Guido

ناشر: IEEE

سال: 2014

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced

نوع: Journal Paper

نویسنده : Condo, Carlo; Martina, Maurizio; Piccinini, G.; Masera, Guido

ناشر: IEEE

سال: 2014

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Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First <inline-formula> <img src="/images/tex/473.gif" alt="W"> </inline-formula> Maximum/Minimum Values

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced

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Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First <inline-formula> <img src="/images/tex/473.gif" alt="W"> </inline-formula> Maximum/Minimum Values

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors

VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced