Search

نمایش تعداد 1-6 از 6

DECO: DIMM controller efficient for ECC operations

نوع: Journal Paper

نویسنده : Wooyoung Jang

ناشر: IET

سال: 2014

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs

نوع: Journal Paper

نویسنده : Azevedo, Joao; Virazel, A.; Bosio, A.; Dilillo, L.; Girard, P.; Todri-Sanial, Aida; Alvarez-Herault, Jeremy; Mackay, Ken

ناشر: IEEE

سال: 2014

Performance optimization of PVM based parallel applications using optimal number of slaves

نوع: Conference Paper

ناشر: IEEE

سال: 2014

Error-Correcting Code Aware Memory Subsystem

نوع: Journal Paper

نویسنده : Wooyoung Jang

ناشر: IEEE

سال: 2014

Column selection solutions for L1 data caches implemented using eight-transistor cells

نوع: Journal Paper

نویسنده : Farahani, Mostafa; Baniasadi, Amirali

ناشر: IET

سال: 2014

<inline-formula> <img src="/images/tex/21634.gif" alt="mathsf{B}^{p}"> </inline-formula>-<inline-formula> <img src="/images/tex/21635.gif" alt="mathsf{Tree}"> </inline-formula>: A Predictive <inline-formula> <img src="/images/tex/21636.gif" alt="mathsf{B}^{+}"> </inline-formula>-<inline-formula> <img src="/images/tex/21635.gif" alt="mathsf{Tree}"> <

نوع: Journal Paper

نویسنده : Weiwei Hu; Guoliang Li; Jiacai Ni; Dalie Sun; Kian-Lee Tan

ناشر: IEEE

سال: 2014

Search

DECO: DIMM controller efficient for ECC operations

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs

Performance optimization of PVM based parallel applications using optimal number of slaves

Error-Correcting Code Aware Memory Subsystem

Column selection solutions for L1 data caches implemented using eight-transistor cells

نویسنده

ناشر

سال

کلیدواژه

نوع

زبان

نوع محتوا

عنوان ناشر

Search

Filters

DECO: DIMM controller efficient for ECC operations

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs

Performance optimization of PVM based parallel applications using optimal number of slaves

Error-Correcting Code Aware Memory Subsystem

Column selection solutions for L1 data caches implemented using eight-transistor cells