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2-tap pre-emphasis SST transmitter with skin effect loss equalisation in 65 nm CMOS technology

Type: Journal Paper

Author : Ke Huang; Ziqiang Wang; Xuqiang Zheng; Chun Zhang; Zhihua Wang

Publisher: IET

Year: 2014

A 40Gbps quarter rate CDR using CMOS-style signal alignment strategy in 65nm CMOS

Type: Journal Paper

Author : Peng Wang; Xuqiang Zheng; Ziqiang Wang; Chun Zhang; Zhihua Wang

Year: 2014

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A 25Gb/s adaptive decision feedback equalizer for 100G Ethernet in 65NM CMOS technology

Type: Conference Paper

Author : Jinxing Guo; Liji Wu; Shuai Yuan; Xuqiang Zheng; Ziqiang Wang

Publisher: IEEE

Year: 2014

A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology

Type: Conference Paper

Author : Ke Huang; Ziqiang Wang; Xuqiang Zheng; Chun Zhang; Zhihua Wang

Publisher: IEEE

Year: 2014

2 GHz sub-harmonically injectin-locked PLL with mixer-based injection timing control in 0.18 μm CMOS technology

Type: Journal Paper

Author : Ke Huang; Ziqiang Wang; Xuqiang Zheng; Chun Zhang; Zhihua Wang

Publisher: IET

Year: 2014

A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology

Type: Journal Paper

Author : Shuai Yuan; Liji Wu; Ziqiang Wang; Xuqiang Zheng; Chun Zhang; Zhihua Wang

Year: 2016

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A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS

Type: Journal Paper

Author : Shijie Hu; Chen Jia; Ke Huang; Chun Zhang; Xuqiang Zheng; Zhihua Wang

Year: 2012

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A 10Gb/s speculative decision feedback equalizer with a novel implementation of adaption in 65nm CMOS technology

Type: Journal Paper

Author : Shuai Yuan; Ziqiang Wang; Xuqiang Zheng; Liji Wu; Chun Zhang; Zhihua Wang

Year: 2014

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A 4.8-mW/Gb/s 9.6-Gb/s 5 <inline-formula> <img src="/images/tex/515.gif" alt="+"> </inline-formula> 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS

Type: Journal Paper

Author : Shuai Yuan; Ziqiang Wang; Xuqiang Zheng; Ke Huang; Ni Xu; Woogeun Rhee; Liji Wu; Chun Zhang

Publisher: IEEE

Year: 2014

A 15Gb/s wireline repeater in 65nm CMOS technology

Type: Journal Paper

Author : Weidong Cao; Xuqiang Zheng; Ziqiang Wang; Dongmei Li; Fule Li; Shigang Yue; Zhihua Wang

Year: 2015

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2-tap pre-emphasis SST transmitter with skin effect loss equalisation in 65 nm CMOS technology

A 40Gbps quarter rate CDR using CMOS-style signal alignment strategy in 65nm CMOS

A 25Gb/s adaptive decision feedback equalizer for 100G Ethernet in 65NM CMOS technology

A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology

2 GHz sub-harmonically injectin-locked PLL with mixer-based injection timing control in 0.18 μm CMOS technology

A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology

A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS

A 10Gb/s speculative decision feedback equalizer with a novel implementation of adaption in 65nm CMOS technology

A 4.8-mW/Gb/s 9.6-Gb/s 5 <inline-formula> <img src="/images/tex/515.gif" alt="+"> </inline-formula> 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS

A 15Gb/s wireline repeater in 65nm CMOS technology

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2-tap pre-emphasis SST transmitter with skin effect loss equalisation in 65 nm CMOS technology

A 40Gbps quarter rate CDR using CMOS-style signal alignment strategy in 65nm CMOS

A 25Gb/s adaptive decision feedback equalizer for 100G Ethernet in 65NM CMOS technology

A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology

2 GHz sub-harmonically injectin-locked PLL with mixer-based injection timing control in 0.18 &#x003BC;m CMOS technology

A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology

A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS

A 10Gb/s speculative decision feedback equalizer with a novel implementation of adaption in 65nm CMOS technology

A 4.8-mW/Gb/s 9.6-Gb/s 5 <inline-formula> <img src="/images/tex/515.gif" alt="+"> </inline-formula> 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS

A 15Gb/s wireline repeater in 65nm CMOS technology

2 GHz sub-harmonically injectin-locked PLL with mixer-based injection timing control in 0.18 μm CMOS technology