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Border Traps in InGaAs nMOSFETs Assessed by Low-Frequency Noise

Type: Journal Paper

Author : Scarpino, Mercedes; Gupta, Swastik; Lin, Dongyang; Alian, A.; Crupi, Felice; Collaert, Nadine; Thean, A.; Simoen, Eddy

Publisher: IEEE

Year: 2014

Unity gain frequency on FinFET and TFET devices

Type: Conference Paper

Author : Agopian, P.G.D.; Martino, J.A.; Vandooren, A.; Rooyackers, R.; Simoen, E.; Thean, A.; Claeys, C.

Publisher: IEEE

Year: 2014

Fast Ramped Voltage Characterization of Single Trap Bias and Temperature Impact on Time-Dependent <inline-formula> <img src="/images/tex/18637.gif" alt="V_{\\rm TH}"> </inline-formula> Variability

Type: Journal Paper

Author : Toledano-Luque, Maria; Degraeve, Robin; Roussel, P.J.; Ragnarsson, Lars-Ake; Chiarella, T.; Horiguchi, Naoto; Mocuta, Anda; Thean, A.

Publisher: IEEE

Year: 2014

A Simplified Method for (Circular) Transmission Line Model Simulation and Ultralow Contact Resistivity Extraction

Type: Journal Paper

Author : Hao Yu; Schaekers, Marc; Schram, T.; Collaert, Nadine; de Meyer, K.; Horiguchi, Naoto; Thean, A.; Barla, Kathy

Publisher: IEEE

Year: 2014

Early voltage and intrinsic voltage gain in vertical nanowire-TFETs as a function of temperature

Type: Conference Paper

Author : Martino, M.D.V.; Neves, F.S.; Agopian, P.G.D.; Martino, J.A.; Vandooren, A.; Rooyackers, R.; Simoen, E.; Thean, A.; Claeys, C.

Publisher: IEEE

Year: 2014

Superior Reliability of Junctionless pFinFETs by Reduced Oxide Electric Field

Type: Journal Paper

Author : Toledano-Luque, Maria; Matagne, Philippe; Sibaja-Hernandez, Arturo; Chiarella, T.; Ragnarsson, Lars-Ake; Soree, Bart; Cho, Moonju; Mocuta, Anda; Thean, A.

Publisher: IEEE

Year: 2014

Low-frequency noise analysis of DRAM peripheral transistors with La cap

Type: Conference Paper

Author : Simoen, E.; Ritzenthaler, R.; Schram, T.; Aoulaiche, M.; Spessot, A.; Fazan, P.; Na, H.-J.; Lee, S.-G.; Son, Y.; Noh, K.B.; Arimura, H.; Horiguchi, N.; Thean, A.; Claeys, C.

Publisher: IEEE

Year: 2014

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

Type: Conference Paper

Author : Bao, T.H.; Yakimets, D.; Ryckaert, J.; Ciofi, I.; Baert, R.; Veloso, A.; Boemmels, J.; Collaert, N.; Roussel, P.; Demuynck, S.; Raghavan, P.; Mercha, A.; Tokei, Z.; Verkest, D.; Thean, A.V.-Y.; Wambacq, P.

Publisher: IEEE

Year: 2014

Untitled

Type: Journal Paper

Author : Rooyackers, R.; Vandooren, A.; Verhulst, A.S.; Walke, A.M.; Simoen, E.; Devriendt, K.; Lo-Corotondo, S.; Demand, M.; Bryce, G.; Loo, R.; Hikavyy, A.; Vandeweyer, T.; Huyghebaert, C.; Collaert, N.; Thean, A.V.Y.

Publisher: IEEE

Year: 2014

Design Technology co-optimization for N10

Type: Conference Paper

Author : Ryckaert, J.; Raghavan, P.; Baert, R.; Bardon, M.G.; Dusa, M.; Mallik, A.; Sakhare, S.; Vandewalle, B.; Wambacq, P.; Chava, B.; Croes, K.; Dehan, M.; Jang, D.; Leray, P.; Liu, T.-T.; Miyaguchi, K.; Parvais, B.; Schuddinck, P.; Weemaes, P.; Mercha, A.; Bommels, J.; Horiguchi, N.; McIntyre, G.; Thean, A.; Tokei, Z.; Cheng, S.; Verkest, D.; Steegen, A.

Publisher: IEEE

Year: 2014

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Border Traps in InGaAs nMOSFETs Assessed by Low-Frequency Noise

Unity gain frequency on FinFET and TFET devices

Fast Ramped Voltage Characterization of Single Trap Bias and Temperature Impact on Time-Dependent <inline-formula> <img src="/images/tex/18637.gif" alt="V_{\\rm TH}"> </inline-formula> Variability

A Simplified Method for (Circular) Transmission Line Model Simulation and Ultralow Contact Resistivity Extraction

Early voltage and intrinsic voltage gain in vertical nanowire-TFETs as a function of temperature

Superior Reliability of Junctionless pFinFETs by Reduced Oxide Electric Field

Low-frequency noise analysis of DRAM peripheral transistors with La cap

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

Untitled

Design Technology co-optimization for N10

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Border Traps in InGaAs nMOSFETs Assessed by Low-Frequency Noise

Unity gain frequency on FinFET and TFET devices

Fast Ramped Voltage Characterization of Single Trap Bias and Temperature Impact on Time-Dependent <inline-formula> <img src="/images/tex/18637.gif" alt="V_{\\rm TH}"> </inline-formula> Variability

A Simplified Method for (Circular) Transmission Line Model Simulation and Ultralow Contact Resistivity Extraction

Early voltage and intrinsic voltage gain in vertical nanowire-TFETs as a function of temperature

Superior Reliability of Junctionless pFinFETs by Reduced Oxide Electric Field

Low-frequency noise analysis of DRAM peripheral transistors with La cap

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

Untitled

Design Technology co-optimization for N10