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Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits

Type: Conference Paper

Author : Beste, M. , Kiamehr, S. , Tahoori, M.B.

Year: 2014

Quantitative evaluation of register vulnerabilities in RTL control paths

Type: Conference Paper

Author : Liang Chen , Ebrahimi, M. , Tahoori, M.B.

Publisher: IEEE

Year: 2014

Physical design of CNTFET-based circuits for yield improvement

Type: Conference Paper

Author : Beste, M.; Kiamehr, S.; Tahoori, M.B.

Publisher: IEEE

Year: 2014

Emerging Non-Volatile Memory technologies for future low power reconfigurable systems

Type: Conference Paper

Author : Ahari, A. , Asadi, H. , Tahoori, M.B.

Publisher: IEEE

Year: 2014

A power-efficient reconfigurable architecture using PCM configuration technology

Type: Conference Paper

Author : Ahari, A.; Asadi, H.; Khaleghi, B.; Tahoori, M.B.

Publisher: IEEE

Year: 2014

Towards dark silicon era in FPGAs using complementary hard logic design

Type: Conference Paper

Author : Ahari, A.; Khaleghi, B.; Ebrahimi, Z.; Asadi, H.; Tahoori, M.B.

Publisher: IEEE

Year: 2014

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Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits

Quantitative evaluation of register vulnerabilities in RTL control paths

Physical design of CNTFET-based circuits for yield improvement

Emerging Non-Volatile Memory technologies for future low power reconfigurable systems

A power-efficient reconfigurable architecture using PCM configuration technology

Towards dark silicon era in FPGAs using complementary hard logic design

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Layout-Aware Delay Variation Optimization for CNTFET-Based Circuits

Quantitative evaluation of register vulnerabilities in RTL control paths

Physical design of CNTFET-based circuits for yield improvement

Emerging Non-Volatile Memory technologies for future low power reconfigurable systems

A power-efficient reconfigurable architecture using PCM configuration technology

Towards dark silicon era in FPGAs using complementary hard logic design