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Proposal of a process design methodology of Fully depleted SOI nMOSFET using only three photolithograph steps for educational application

Type: Conference Paper

Author : Rangel, R.C.; Martino, J.A.

Publisher: IEEE

Year: 2014

Field effect transistors: From mosfet to Tunnel-Fet analog performance perspective

Type: Conference Paper

Author : Martino, J.A.; Agopian, P.G.D.; Simoen, E.; Claeys, C.

Publisher: IEEE

Year: 2014

Graphene for advanced devices applications

Type: Conference Paper

Author : Sivieri, V.B.; Wessely, P.J.; Schwalke, U.; Agopian, P.G.D.; Martino, J.A.

Publisher: IEEE

Year: 2014

Drain induced barrier thinning on TFETs with different source/drain engineering

Type: Conference Paper

Author : Martino, M.D.V.; Martino, J.A.; Agopian, P.G.D.

Publisher: IEEE

Year: 2014

Influence of high temperature on substrate effect of UTBB SOI nMOSFETs

Type: Conference Paper

Author : Itocazu, V.T.; Sonnenberg, V.; Simoen, E.; Claeys, C.; Martino, J.A.

Publisher: IEEE

Year: 2014

Silicon film thickness influence on enhanced dynamic threshold UTBB SOI nMOSFETs

Type: Conference Paper

Author : Sasaki, K.R.A.; Aoulaiche, M.; Simoen, E.; Claeys, C.; Martino, J.A.

Publisher: IEEE

Year: 2014

Comparison of analog performance between SOI and Bulk pFinFET

Type: Conference Paper

Author : Oliveira, A.V.; Agopian, P.G.D.; Simoen, E.; Claeys, C.; Martino, J.A.

Publisher: IEEE

Year: 2014

Influence of underlap on UTBB SOI MOSFETs in dynamic threshold mode

Type: Conference Paper

Author : Sasaki, K.R.A.; Aoulaiche, M.; Simoen, E.; Claeys, C.; Martino, J.A.

Publisher: IEEE

Year: 2014

Fin width influence on analog performance of SOI and bulk FINFETs

Type: Conference Paper

Author : Oliveira, A.V.; Agopian, P.G.D.; Martino, J.A.; Simoen, E.; Claeys, C.

Publisher: IEEE

Year: 2014

Floating body effect on n-channel bulk FinFETs for memory application

Type: Conference Paper

Author : Andrade, M.G.C.; Almeida, L.M.; Martino, J.A.; Aoulaiche, M.; Simoen, E.; Claeys, C.

Publisher: IEEE

Year: 2014

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Proposal of a process design methodology of Fully depleted SOI nMOSFET using only three photolithograph steps for educational application

Field effect transistors: From mosfet to Tunnel-Fet analog performance perspective

Graphene for advanced devices applications

Drain induced barrier thinning on TFETs with different source/drain engineering

Influence of high temperature on substrate effect of UTBB SOI nMOSFETs

Silicon film thickness influence on enhanced dynamic threshold UTBB SOI nMOSFETs

Comparison of analog performance between SOI and Bulk pFinFET

Influence of underlap on UTBB SOI MOSFETs in dynamic threshold mode

Fin width influence on analog performance of SOI and bulk FINFETs

Floating body effect on n-channel bulk FinFETs for memory application

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Proposal of a process design methodology of Fully depleted SOI nMOSFET using only three photolithograph steps for educational application

Field effect transistors: From mosfet to Tunnel-Fet analog performance perspective

Graphene for advanced devices applications

Drain induced barrier thinning on TFETs with different source/drain engineering

Influence of high temperature on substrate effect of UTBB SOI nMOSFETs

Silicon film thickness influence on enhanced dynamic threshold UTBB SOI nMOSFETs

Comparison of analog performance between SOI and Bulk pFinFET

Influence of underlap on UTBB SOI MOSFETs in dynamic threshold mode

Fin width influence on analog performance of SOI and bulk FINFETs

Floating body effect on n-channel bulk FinFETs for memory application