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Practical problems in VLSI physical design automation

Type: Ebook

Author : Sung Kyu Lim

Publisher: Springer

Year: 2008

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

Type: Ebook

Author : Sung Kyu Lim (auth.)

Publisher: Springer New York

Year: 2013

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Scan chain and power delivery network synthesis for pre-bond test of 3D ICs

Type: Conference Paper

Author : Shreepad Panth; Sung Kyu Lim

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Reliability and performance-aware 3D SRAM design

Type: Journal Paper

Author : Mohit Pathak; Sung Kyu Lim

Year: 2011

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Potential Freeway Congestion Severity Measure: Impact of Continuous Congestion Patterns

Type: Journal Paper

Author : Jungwook Jun; In-Kyu Lim

Year: 2009

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Transient drain current and propagation delay in SOI CMOS

Type: Journal Paper

Author : Hyung Kyu Lim; Fossum, J.G.

Year: 1984

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On GPU bus power reduction with 3D IC technologies

Type: Conference Paper

Author : Young-Joon Lee , Sung Kyu Lim

Publisher: IEEE

Year: 2014

Dynamic Configuration of SSD File Management

Type: Conference Paper

Author : Hyuk-Kyu Lim , Je-Ho Park

Publisher: IEEE

Year: 2014

Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement

Type: Journal Paper

Author : Athikulwongse, Krit; Ekpanyapong, M.; Sung Kyu Lim

Publisher: IEEE

Year: 2014

Fast and accurate full-chip extraction and optimization of TSV-to-wire coupling

Type: Conference Paper

Author : Peng, Yarui , Petranovic, Dusan , Sung Kyu Lim

Publisher: IEEE

Year: 2014

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Practical problems in VLSI physical design automation

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

Scan chain and power delivery network synthesis for pre-bond test of 3D ICs

Reliability and performance-aware 3D SRAM design

Potential Freeway Congestion Severity Measure: Impact of Continuous Congestion Patterns

Transient drain current and propagation delay in SOI CMOS

On GPU bus power reduction with 3D IC technologies

Dynamic Configuration of SSD File Management

Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement

Fast and accurate full-chip extraction and optimization of TSV-to-wire coupling

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Practical problems in VLSI physical design automation

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

Scan chain and power delivery network synthesis for pre-bond test of 3D ICs

Reliability and performance-aware 3D SRAM design

Potential Freeway Congestion Severity Measure: Impact of Continuous Congestion Patterns

Transient drain current and propagation delay in SOI CMOS

On GPU bus power reduction with 3D IC technologies

Dynamic Configuration of SSD File Management

Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement

Fast and accurate full-chip extraction and optimization of TSV-to-wire coupling