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Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors

Type: Journal Paper

Author : Khan, O.; Kundu, S.

Year: 2010

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A generic and efficient modeling of phase margin of high performance CMOS OpAmps

Type: Conference Paper

Author : Kundu, S. , Mandal, P.

Publisher: IEEE

Year: 2014

A modified BP network using malsburg learning for rotation and location invariant fingerprint recognition and localization with and without occlusion

Type: Conference Paper

Author : Kundu, S. , Sarker, G.

Publisher: IEEE

Year: 2014

Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip

Type: Conference Paper

Author : Phanibhushana, B. , Kundu, S.

Publisher: IEEE

Year: 2014

Glitch Power Reduction via Clock Skew Scheduling

Type: Conference Paper

Author : Vijayakumar, A. , Kundu, S.

Publisher: IEEE

Year: 2014

Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core

Type: Conference Paper

Author : Rodrigues, R. , Koren, I. , Kundu, S.

Year: 2014

On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions

Type: Conference Paper

Author : Kumar, R. , Dhanuskodi, S.N. , Kundu, S.

Year: 2014

Outage and SEP of secondary user with imperfect channel estimation and primary user interference

Type: Conference Paper

Author : Prasad, B. , Roy, S.D. , Kundu, S.

Year: 2014

Gain and SAR improvement of a conventional patch antenna using a novel Pi-shaped DNG metamaterial

Type: Conference Paper

Author : Mallik, A. , Kundu, S. , Goni, M.O.

Publisher: IEEE

Year: 2014

Small monopole antenna with corner modified patch for UWB applications

Type: Conference Paper

Author : Kundu, S. , Kundu, M. , Mandal, K.

Publisher: IEEE

Year: 2014

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Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors

A generic and efficient modeling of phase margin of high performance CMOS OpAmps

A modified BP network using malsburg learning for rotation and location invariant fingerprint recognition and localization with and without occlusion

Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip

Glitch Power Reduction via Clock Skew Scheduling

Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core

On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions

Outage and SEP of secondary user with imperfect channel estimation and primary user interference

Gain and SAR improvement of a conventional patch antenna using a novel Pi-shaped DNG metamaterial

Small monopole antenna with corner modified patch for UWB applications

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Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors

A generic and efficient modeling of phase margin of high performance CMOS OpAmps

A modified BP network using malsburg learning for rotation and location invariant fingerprint recognition and localization with and without occlusion

Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip

Glitch Power Reduction via Clock Skew Scheduling

Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core

On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions

Outage and SEP of secondary user with imperfect channel estimation and primary user interference

Gain and SAR improvement of a conventional patch antenna using a novel Pi-shaped DNG metamaterial

Small monopole antenna with corner modified patch for UWB applications