Search
Now showing items 1-4 of 4
A 3.15pJ/cyc 32-bit RISC CPU with timing-error prevention and adaptive clocking in 28nm CMOS
Publisher: IEEE
Year: 2014
A 2.5-GHz 4.2-dB NF direct ΔΣ receiver with a frequency-translating integrator
Publisher: IEEE
Year: 2014



CSV
RIS