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Joint estimation for Carrier Frequency Offset and Sampling Frequency Offset in OFDM systems

Type: Conference Paper

Author : Jing Lin; Fan Ye; Junyan Ren

Publisher: IEEE

Year: 2014

A 32.5-GS/s Sampler With Time-Interleaved Track-and-Hold Amplifier in 65-nm CMOS

Type: Journal Paper

Author : Shunli Ma; Hao Yu; Junyan Ren

Publisher: IEEE

Year: 2014

A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators

Type: Journal Paper

Author : Guoxian Dai; Chixiao Chen; Shunli Ma; Fan Ye; Junyan Ren

Year: 2014

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An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units

Type: Journal Paper

Author : Weizhen Wang; Hao Zhou; Fan Ye; Junyan Ren

Year: 2015

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A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC

Type: Journal Paper

Author : Jian Mei; Jixuan Xiang; Huabin Chen; Fan Ye; Junyan Ren

Year: 2013

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[IEEE 2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT) - Beijing, China (2008.10.20-2008.10.23)] 2008 9th International Conference on Solid-State and Integrated-Circuit Technology - A 260 MHz 5^th-order Gm-C Biquad Low-Pass filter with wide frequency tuning range

Type: Journal Paper

Author : Jinhan Fan,; Wei Li,; Ning Li,; Junyan Ren,

Year: 2008

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A 32.5-GS/s two-channel time-interleaved CMOS sampler with switched-source follower based track-and-hold amplifier

Type: Conference Paper

Author : Shunli Ma , Jiacheng Wang , Hao Yu , Junyan Ren

Publisher: IEEE

Year: 2014

A 60.8–67GHz and 6.3mW injection-locked frequency divider with switching-inductor loaded transformer in 65nm CMOS

Type: Conference Paper

Author : Haipeng Fu , Wei Fei , Hao Yu , Junyan Ren

Publisher: IEEE

Year: 2014

A background time-skew calibration for flash-assisted time-interleaved SAR ADCS with redundant check bit

Type: Conference Paper

Author : Sijia Ma; Yongzhen Chen; Fan Ye; Junyan Ren

Publisher: IEEE

Year: 2014

A 500-1000MS/s 12-bit resolution level-shift bootstrapped switch

Type: Conference Paper

Author : Jingjing Wang; Chixiao Chen; Zemin Feng; Fan Ye; Junyan Ren

Publisher: IEEE

Year: 2014

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Joint estimation for Carrier Frequency Offset and Sampling Frequency Offset in OFDM systems

A 32.5-GS/s Sampler With Time-Interleaved Track-and-Hold Amplifier in 65-nm CMOS

A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators

An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units

A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC

A 32.5-GS/s two-channel time-interleaved CMOS sampler with switched-source follower based track-and-hold amplifier

A 60.8–67GHz and 6.3mW injection-locked frequency divider with switching-inductor loaded transformer in 65nm CMOS

A background time-skew calibration for flash-assisted time-interleaved SAR ADCS with redundant check bit

A 500-1000MS/s 12-bit resolution level-shift bootstrapped switch

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Joint estimation for Carrier Frequency Offset and Sampling Frequency Offset in OFDM systems

A 32.5-GS/s Sampler With Time-Interleaved Track-and-Hold Amplifier in 65-nm CMOS

A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators

An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units

A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC

A 32.5-GS/s two-channel time-interleaved CMOS sampler with switched-source follower based track-and-hold amplifier

A 60.8&#x2013;67GHz and 6.3mW injection-locked frequency divider with switching-inductor loaded transformer in 65nm CMOS

A background time-skew calibration for flash-assisted time-interleaved SAR ADCS with redundant check bit

A 500-1000MS/s 12-bit resolution level-shift bootstrapped switch

A 60.8–67GHz and 6.3mW injection-locked frequency divider with switching-inductor loaded transformer in 65nm CMOS