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[IEEE 2011 IEEE 29th International Conference on Computer Design (ICCD 2011) - Amherst, MA, USA (2011.10.9-2011.10.12)] 2011 IEEE 29th International Conference on Computer Design (ICCD) - 3D vs. 2D analysis of FinFET logic gates under process variations

Type: Journal Paper

Author : Chaudhuri, Sourindra; Jha, Niraj K.

Year: 2011

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FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations

Type: Journal Paper

Author : Yang Yang; Jha, Niraj K.

Publisher: IEEE

Year: 2014

[IEEE 2013 26th International Conference on VLSI Design: concurrently with the 12th International Conference on Embedded Systems - Pune, India (2013.01.5-2013.01.10)] 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems - Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations

Type: Journal Paper

Author : Yang, Yang; Jha, Niraj K.

Year: 2013

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Design of Logic Gates and Flip-Flops in High-performance FinFET Technology

Type: Journal Paper

Author : Bhoj, Ajay N.; Jha, Niraj K.

Publisher: IEEE

Year: 2013

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Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs

Type: Journal Paper

Author : Bhoj, Ajay N.; Jha, Niraj K.

Publisher: IEEE

Year: 2014

FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks

Type: Journal Paper

Author : Chun-Yi Lee; Jha, Niraj K.

Publisher: IEEE

Year: 2014

A Trusted Virtual Machine in an Untrusted Management Environment

Type: Journal Paper

Author : Li, Chunxiao; Raghunathan, Anand; Jha, Niraj K.

Year: 2012

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Trustworthiness of Medical Devices and Body Area Networks

Type: Journal Paper

Author : Meng Zhang; Raghunathan, Anand; Jha, Niraj K.

Publisher: IEEE

Year: 2014

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems

Type: Journal Paper

Author : Luo, Jiong; Jha, Niraj K.; Peh, Li-Shiuan

Year: 2007

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FTQLS: Fault-Tolerant Quantum Logic Synthesis

Type: Journal Paper

Author : Chia-Chun Lin; Chakrabarti, Anandaroop; Jha, Niraj K.

Publisher: IEEE

Year: 2014

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[IEEE 2011 IEEE 29th International Conference on Computer Design (ICCD 2011) - Amherst, MA, USA (2011.10.9-2011.10.12)] 2011 IEEE 29th International Conference on Computer Design (ICCD) - 3D vs. 2D analysis of FinFET logic gates under process variations

FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations

Design of Logic Gates and Flip-Flops in High-performance FinFET Technology

Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs

FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks

A Trusted Virtual Machine in an Untrusted Management Environment

Trustworthiness of Medical Devices and Body Area Networks

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems

FTQLS: Fault-Tolerant Quantum Logic Synthesis

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[IEEE 2011 IEEE 29th International Conference on Computer Design (ICCD 2011) - Amherst, MA, USA (2011.10.9-2011.10.12)] 2011 IEEE 29th International Conference on Computer Design (ICCD) - 3D vs. 2D analysis of FinFET logic gates under process variations

FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations

Design of Logic Gates and Flip-Flops in High-performance FinFET Technology

Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs

FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks

A Trusted Virtual Machine in an Untrusted Management Environment

Trustworthiness of Medical Devices and Body Area Networks

Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems

FTQLS: Fault-Tolerant Quantum Logic Synthesis