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CMOS switched-op-amp-based sample-and-hold circuit

Type: Journal Paper

Author : Liang Dai; Harjani, R.

Year: 2000

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[IEEE 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA, USA (5-7 Feb. 2001)] 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) - A +18 dBm IIP3 LNA in 0.35 Î¼m CMOS

Type: Journal Paper

Author : Yongwang Ding,; Harjani, R.

Year: 2001

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A unified framework for capacitive series-parallel DC-DC converter design

Type: Conference Paper

Author : Harjani, R.; Chaubey, S.

Publisher: IEEE

Year: 2014

A High-Efficiency DC–DC Converter Using 2 nH Integrated Inductors

Type: Journal Paper

Author : Wibben, J.; Harjani, R.

Year: 2008

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Design of low-phase-noise CMOS ring oscillators

Type: Journal Paper

Author : Liang Dai; Harjani, R.

Year: 2002

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Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range

Type: Journal Paper

Author : Kudva, S.S.; Harjani, R.

Publisher: IEEE

Year: 2011

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High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS

Type: Conference Paper

Author : Palani, R.K.; Harjani, R.

Publisher: IEEE

Year: 2014

A 5 Gbps 0.13 m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links

Type: Journal Paper

Author : Ahmadi, M.R.; Amirkhany, A.; Harjani, R.

Publisher: IEEE

Year: 2010

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A 2.5nJ/bit multiband (MBAN & ISM) transmitter for IEEE 802.15.6 based on a hybrid polyphase-MUX/ILO based modulator

Type: Conference Paper

Author : Rahman, M. , Elbadry, M. , Harjani, R.

Publisher: IEEE

Year: 2014

High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS

Type: Conference Paper

Author : Kudva, S.; Chaubey, S.; Harjani, R.

Publisher: IEEE

Year: 2014

Search

CMOS switched-op-amp-based sample-and-hold circuit

[IEEE 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA, USA (5-7 Feb. 2001)] 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) - A +18 dBm IIP3 LNA in 0.35 Î¼m CMOS

A unified framework for capacitive series-parallel DC-DC converter design

A High-Efficiency DC–DC Converter Using 2 nH Integrated Inductors

Design of low-phase-noise CMOS ring oscillators

Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range

High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS

A 5 Gbps 0.13 m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links

A 2.5nJ/bit multiband (MBAN & ISM) transmitter for IEEE 802.15.6 based on a hybrid polyphase-MUX/ILO based modulator

High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS

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CMOS switched-op-amp-based sample-and-hold circuit

[IEEE 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA, USA (5-7 Feb. 2001)] 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) - A +18 dBm IIP3 LNA in 0.35 Î¼m CMOS

A unified framework for capacitive series-parallel DC-DC converter design

A High-Efficiency DC–DC Converter Using 2 nH Integrated Inductors

Design of low-phase-noise CMOS ring oscillators

Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range

High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS

A 5 Gbps 0.13 m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links

A 2.5nJ/bit multiband (MBAN &amp; ISM) transmitter for IEEE 802.15.6 based on a hybrid polyphase-MUX/ILO based modulator

High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS

A 2.5nJ/bit multiband (MBAN & ISM) transmitter for IEEE 802.15.6 based on a hybrid polyphase-MUX/ILO based modulator