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A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm<sup>2</sup> in 32 nm SOI CMOS

Type: Conference Paper

Author : Kull, Lukas; Pliva, Jan; Toifl, Thomas; Schmatz, Martin; Francese, Pier Andrea; Menolfi, Christian; Braendli, Matthias; Kossel, Marcel; Morf, Thomas; Andersen, Toke Meyer; Leblebici, Yusuf

Publisher: IEEE

Year: 2014

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology

Type: Journal Paper

Author : Gangasani, Gautam R.; Chun-Ming Hsu; Bulzacchelli, John F.; Beukema, Troy; Kelly, Wayne; Xu, Hui H.; Freitas, David; Prati, Andrea; Gardellini, Daniele; Reutemann, Robert; Cervelli, Giovanni; Hertle, Juergen; Baecher, Matthew; Garlett, Jon; Francese, Pier-Andrea; Ewen, John F.; Hanson, D.; Storaska, Daniel W.; Meghelli, Mounir

Publisher: IEEE

Year: 2014

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A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm<sup>2</sup> in 32 nm SOI CMOS

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology

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A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm<sup>2</sup> in 32 nm SOI CMOS

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology