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A fractional-N DPLL with adaptive spur cancellation and calibration-free injection-locked TDC in 65nm CMOS

Type: Conference Paper

Author : Cheng-Ru Ho , Chen, M.S.-W.

Publisher: IEEE

Year: 2014

Calculation of Energy Losses in a Distribution System

Type: Journal Paper

Author : Sun, D.I.H.; Abe, S.; Shoults, R.R.; Chen, M.S.; Eichenberger, P.; Farris, D.

Year: 1980

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A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS

Type: Conference Paper

Author : Shiyu Su , Tu-I Tsai , Sharma, P. , Chen, M.S.-W.

Publisher: IEEE

Year: 2014

Wireless Power Transfer Communications for Leg Lengthening/Shortening Procedures

Type: Conference Paper

Author : Sum, Y.L.; Soong, B.H.; Liu, W.; Chen, M.S.

Publisher: IEEE

Year: 2014

Distribution system power flow analysis-a rigid approach

Type: Journal Paper

Author : Chen, T.-H.; Chen, M.-S.; Hwang, K.-J.; Kotas, P.; Chebli, E.A.

Year: 1991

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On-Line Contingency Selection Algorithm for Voltage Security Analysis

Type: Journal Paper

Author : Nara, K.; Tanaka, K.; Kodama, H.; Shoults, R.R.; Chen, M.S.; Van Olinda, P.; Bertagnolli, D.

Year: 1985

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A fractional-N DPLL with adaptive spur cancellation and calibration-free injection-locked TDC in 65nm CMOS

Calculation of Energy Losses in a Distribution System

A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS

Wireless Power Transfer Communications for Leg Lengthening/Shortening Procedures

Distribution system power flow analysis-a rigid approach

On-Line Contingency Selection Algorithm for Voltage Security Analysis

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A fractional-N DPLL with adaptive spur cancellation and calibration-free injection-locked TDC in 65nm CMOS

Calculation of Energy Losses in a Distribution System

A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving &#x003E;75dB SFDR over 500MHz in 65nm CMOS

Wireless Power Transfer Communications for Leg Lengthening/Shortening Procedures

Distribution system power flow analysis-a rigid approach

On-Line Contingency Selection Algorithm for Voltage Security Analysis

A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS