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[IEEE 2011 IEEE 6th International Design and Test Workshop (IDT) - Beirut, Lebanon (2011.12.11-2011.12.14)] 2011 IEEE 6th International Design and Test Workshop (IDT) - Survey of fault tolerance techniques for shared memory multicore/multiprocessor systems

Type: Journal Paper

Author : Mushtaq, Hamid; Al-Ars, Zaid; Bertels, Koen

Year: 2011

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[IEEE 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Tallinn, Estonia (2012.04.18-2012.04.20)] 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - A user-level library for fault tolerance on shared memory multicore systems

Type: Journal Paper

Author : Mushtaq, Hamid; Al-Ars, Zaid; Bertels, Koen

Year: 2012

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[IEEE 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines - Charlotte, NC, USA (2010.05.2-2010.05.4)] 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines - A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems

Type: Journal Paper

Author : Lu, Yi; Marconi, Thomas; Bertels, Koen; Gaydadjiev, Georgi

Year: 2010

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Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication Profiling

Type: Conference Paper

Author : Pham-Quoc, Cuong; Al-Ars, Zaid; Bertels, Koen

Publisher: IEEE

Year: 2014

Region Disjoint Paths in a Class of Optimal Line Graph Networks

Type: Conference Paper

Author : Joshi, Prashant D.; Sen, Arunabha; Hamdioui, Said; Bertels, Koen

Publisher: IEEE

Year: 2014

High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain

Type: Conference Paper

Author : Nane, Razvan; Sima, Vlad Mihai; Quoc, Cuong Pham; Goncalves, Fernando; Bertels, Koen

Publisher: IEEE

Year: 2014

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[IEEE 2011 IEEE 6th International Design and Test Workshop (IDT) - Beirut, Lebanon (2011.12.11-2011.12.14)] 2011 IEEE 6th International Design and Test Workshop (IDT) - Survey of fault tolerance techniques for shared memory multicore/multiprocessor systems

Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication Profiling

Region Disjoint Paths in a Class of Optimal Line Graph Networks

High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain

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[IEEE 2011 IEEE 6th International Design and Test Workshop (IDT) - Beirut, Lebanon (2011.12.11-2011.12.14)] 2011 IEEE 6th International Design and Test Workshop (IDT) - Survey of fault tolerance techniques for shared memory multicore/multiprocessor systems

Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication Profiling

Region Disjoint Paths in a Class of Optimal Line Graph Networks

High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain