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Author : Baschirotto, A.; Bietti, Ivan; Cesura, Giovanni; Colli, Gianluca; Liscidini, Antonio; Nagari, Angelo; Rezzi, Francesco; Svelto, Francesco

Publisher: IEEE

Year: 2014

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Type: Journal Paper

Author : Baschirotto, A.; Campi, F.; Castello, R.; Cesura, G.; Guerrieri, R.; Lavagno, L.; Lodi, A.; Malcovati, P.; Toma, M.

Year: 2006

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Rinaldo Castello: Designer and Teacher [Guest Editorial]

Continuous time analog filters design in ultra-deep-sub-1µm CMOS technologies

A 65-nm, 1-A Buck Converter With Multi-Function SAR-ADC-Based CCM/PSK Digital Control Loop

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

[IEEE 2005 European Conference on Circuit Theory and Design, 2005. - Cork, Ireland (29th August - 1st September 2005)] Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. - A systematic design procedure for high-speed opamp performance optimization

[IEEE 2013 International Conference on IC Design & Technology (ICICDT) - Pavia, Italy (2013.05.29-2013.05.31)] Proceedings of 2013 International Conference on IC Design & Technology (ICICDT) - A 14-bit extended-range incremental ΣΔ ADC matlab-model based on 90nm CMOS-technology

Behavioral modeling of switched-capacitor sigma-delta modulators

[IEEE ISCAS'99. 1999 IEEE International Symposium on Circuits and Systems. VLSI - Orlando, FL, USA (30 May-2 June 1999)] ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349) - Modeling sigma-delta modulator non-idealities in SIMULINK(R)

Designing Analog IC at University of Pavia

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

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Rinaldo Castello: Designer and Teacher [Guest Editorial]

Continuous time analog filters design in ultra-deep-sub-1&#x00B5;m CMOS technologies

A 65-nm, 1-A Buck Converter With Multi-Function SAR-ADC-Based CCM/PSK Digital Control Loop

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

[IEEE 2005 European Conference on Circuit Theory and Design, 2005. - Cork, Ireland (29th August - 1st September 2005)] Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005. - A systematic design procedure for high-speed opamp performance optimization

[IEEE 2013 International Conference on IC Design & Technology (ICICDT) - Pavia, Italy (2013.05.29-2013.05.31)] Proceedings of 2013 International Conference on IC Design & Technology (ICICDT) - A 14-bit extended-range incremental ΣΔ ADC matlab-model based on 90nm CMOS-technology

Behavioral modeling of switched-capacitor sigma-delta modulators

[IEEE ISCAS'99. 1999 IEEE International Symposium on Circuits and Systems. VLSI - Orlando, FL, USA (30 May-2 June 1999)] ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349) - Modeling sigma-delta modulator non-idealities in SIMULINK(R)

Designing Analog IC at University of Pavia

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Continuous time analog filters design in ultra-deep-sub-1µm CMOS technologies