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A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC
Year: 2011
Abstract:
A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital ...
Linearity Enhancement in Digital-to-Analog Converters Using a Modified Decoding Architecture
Year: 2010
Abstract:
This paper describes a new decoding architecture used in segmented D/A Converters. In this architecture, the array of unit elements has been divided into four similar sub-arrays and binary to thermometry conversion is ...
Analysis of the Effect of DAC Resolution on AC Voltage Generated by Digitally Synthesized Source
Publisher: IEEE
Year: 2014
Geometrical positioning with selective hybrid RSSD/AOA weighting AML algorithm for NLOS localization
Publisher: IEEE
Year: 2014
Data cleaning and outlier removal: Application in human skin detection
Publisher: IEEE
Year: 2014
[Front matter]
Publisher: IEEE
Year: 2014
Robust precoding for network MIMO with hierarchical CSIT
Publisher: IEEE
Year: 2014
Visibility-oriented coverage control of mobile robotic networks on non-convex regions
Publisher: IEEE
Year: 2014
Digital Assistant Power Integrated Technologies for PMU in Scaling CMOS Process
Publisher: IEEE
Year: 2014