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RISA 10-Gb/s Low-Power Low-Voltage CTLE Using Gate and Bulk Driven Transistors
Year: 2016
Abstract:
The continuous time linear equalizer (CTLE) which compensates for the high frequency loss of electrical channels is one of the key components in the design of digital serializer / desrializer (SerDes) circuits. A new technique is described...
Hybrid history-based test overlapping to reduce test application time
Publisher: IEEE
Year: 2014
Compiler-driven dynamic reliability management for on-chip systems under variabilities
Publisher: IEEE
Year: 2014
A layered approach for testing timing in the model-based implementation
Publisher: IEEE
Year: 2014
Defect evaluation using the phase information of an EC-GMR sensor
Publisher: IEEE
Year: 2014
Bridging the Gap between Spatial Data Sources and Mashup Applications
Publisher: IEEE
Year: 2014
Miniaturized energy-harvesting piezoelectric chargers
Publisher: IEEE
Year: 2014
An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS
Publisher: IEEE
Year: 2014