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Simulation research of idle damping control for vehicle engine based on PMSM

Type: Conference Paper

Author : Haiyun Zhang; Youtong Zhang; Xiaokun Sun

Publisher: IEEE

Year: 2014

Reconfigurable Computing, 3D Integration, and Recognizing Leaders in our Field

Type: Journal Paper

Author : Altman, Erik R.

Publisher: IEEE

Year: 2014

A low phase noise CMOS voltage-controlled differential ring oscillator

Type: Conference Paper

Author : Rahul, R.; Thilagavathy, R.

Publisher: IEEE

Year: 2014

Analytical, Numerical-, and Measurement–Based Methods for Extracting the Electrical Parameters of Through Silicon Vias (TSVs)

Type: Journal Paper

Author : Ndip, Ivan; Zoschke, K.; Lobbicke, Kai; Wolf, M.J.; Guttowski, Stephan; Reichl, Herbert; Lang, K.-D.; Henke, Heino

Publisher: IEEE

Year: 2014

Fabrication and Testing of a TSV-Enabled Si Interposer With Cu- and Polymer-Based Multilevel Metallization

Type: Journal Paper

Author : Lannon, J.; Hilton, Adrian; Huffman, Alan; Butler, Mairead; Malta, D.; Gregory, Chris; Temple, D.

Publisher: IEEE

Year: 2014

Design, Fabrication, and Characterization of Ultrathin 3-D Glass Interposers With Through-Package-Vias at Same Pitch as TSVs in Silicon

Type: Journal Paper

Author : Sukumaran, Vijay; Kumar, Girish; Ramachandran, Kishore; Suzuki, Yuya; Demir, Kubilay; Sato, Yuuki; Seki, Takaya; Sundaram, Venky; Tummala, Rao R.

Publisher: IEEE

Year: 2014

Remote sensing of sea ice cover using SuperDARN HF radars

Type: Conference Paper

Author : Thomas, E.G.; Sterne, K.T.; Ponomarenko, P.V.; Baker, J.B.H.; Michael Ruohoniemi, J.

Publisher: IEEE

Year: 2014

A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories

Type: Journal Paper

Author : Changwook Lee; Wooheon Kang; Donkoo Cho; Sungho Kang

Publisher: IEEE

Year: 2014

Accurate Formulas for the Capacitance of Tapered-Through Silicon Vias in 3-D ICs

Type: Journal Paper

Author : Qijun Lu; Zhangming Zhu; Yintang Yang; Ruixue Ding

Publisher: IEEE

Year: 2014

Power-aware floorplanning-based power throughsilicon- via technology and bump minimisation for three-dimensional power delivery network

Type: Journal Paper

Author : Cheoljon Jang; Jaehwan Kim; Jongwha Chong

Publisher: IET

Year: 2014

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Simulation research of idle damping control for vehicle engine based on PMSM

Reconfigurable Computing, 3D Integration, and Recognizing Leaders in our Field

A low phase noise CMOS voltage-controlled differential ring oscillator

Analytical, Numerical-, and Measurement–Based Methods for Extracting the Electrical Parameters of Through Silicon Vias (TSVs)

Fabrication and Testing of a TSV-Enabled Si Interposer With Cu- and Polymer-Based Multilevel Metallization

Design, Fabrication, and Characterization of Ultrathin 3-D Glass Interposers With Through-Package-Vias at Same Pitch as TSVs in Silicon

Remote sensing of sea ice cover using SuperDARN HF radars

A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories

Accurate Formulas for the Capacitance of Tapered-Through Silicon Vias in 3-D ICs

Power-aware floorplanning-based power throughsilicon- via technology and bump minimisation for three-dimensional power delivery network

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Simulation research of idle damping control for vehicle engine based on PMSM

Reconfigurable Computing, 3D Integration, and Recognizing Leaders in our Field

A low phase noise CMOS voltage-controlled differential ring oscillator

Analytical, Numerical-, and Measurement&#x2013;Based Methods for Extracting the Electrical Parameters of Through Silicon Vias (TSVs)

Fabrication and Testing of a TSV-Enabled Si Interposer With Cu- and Polymer-Based Multilevel Metallization

Design, Fabrication, and Characterization of Ultrathin 3-D Glass Interposers With Through-Package-Vias at Same Pitch as TSVs in Silicon

Remote sensing of sea ice cover using SuperDARN HF radars

A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories

Accurate Formulas for the Capacitance of Tapered-Through Silicon Vias in 3-D ICs

Power-aware floorplanning-based power throughsilicon- via technology and bump minimisation for three-dimensional power delivery network

Analytical, Numerical-, and Measurement–Based Methods for Extracting the Electrical Parameters of Through Silicon Vias (TSVs)