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Now showing items 1-10 of 61

Temperature Sensing RRAM Architecture for 3-D ICs

Type: Journal Paper

Author : Merkel, Cory E.; Kudithipudi, Dhireesha

Publisher: IEEE

Year: 2014

A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory

Type: Journal Paper

Author : Yi Wang; Zili Shao; Chan, Henry; Bathen, L.A.D.; Dutt, N.D.

Publisher: IEEE

Year: 2014

An Equation-Based Circuit Model and Its Generation Tool for 3-D IC Power Delivery Networks With an Emphasis on Coupling Effect

Type: Journal Paper

Author : Chi-Hsuan Cheng; Tai-Yu Cheng; Cheng-Han Du; Yi-Chang Lu; Yih-Peng Chiou; Liu, Siyuan; Tzong-Lin Wu

Publisher: IEEE

Year: 2014

Metrology and Inspection Requirements for Successful Stacking of Integrated Circuits

Type: Journal Paper

Author : Halder, Sebastian; Miller, Alice; Van Puymbroeck, Jan; Nieuborg, Nancy; Beyne, Eric

Publisher: IEEE

Year: 2014

Flow and rank correlation based detection against Distributed Reflection Denial of Service attack

Type: Conference Paper

Author : Revathi, P.

Publisher: IEEE

Year: 2014

Parasitic Back-Gate Effect in 3-D Fully Depleted Silicon on Insulator Integrated Circuits

Type: Journal Paper

Author : Gaynor, Brad D.; Hassoun, Soha

Publisher: IEEE

Year: 2014

Characterization of the Proximity Effect From Tungsten TSVs on 130-nm CMOS Devices in 3-D ICs

Type: Journal Paper

Author : Sangwook Han; Wentzloff, David D.

Publisher: IEEE

Year: 2014

Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability

Type: Journal Paper

Author : Rab, Muhammad Tauseef; Bawa, Asad Amin; Touba, Nur /A/.

Publisher: IEEE

Year: 2014

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits

Type: Journal Paper

Author : Chun-Yi Kuo; Chi-Jih Shih; Yi-Chang Lu; Li, James Chien-Mo; Chakrabarty, Krishnendu

Publisher: IEEE

Year: 2014

L1–L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters

Type: Journal Paper

Author : Jolondz, Alexei; Weiss, Steven; Golander, A.

Publisher: IEEE

Year: 2014

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Temperature Sensing RRAM Architecture for 3-D ICs

A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory

An Equation-Based Circuit Model and Its Generation Tool for 3-D IC Power Delivery Networks With an Emphasis on Coupling Effect

Metrology and Inspection Requirements for Successful Stacking of Integrated Circuits

Flow and rank correlation based detection against Distributed Reflection Denial of Service attack

Parasitic Back-Gate Effect in 3-D Fully Depleted Silicon on Insulator Integrated Circuits

Characterization of the Proximity Effect From Tungsten TSVs on 130-nm CMOS Devices in 3-D ICs

Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits

L1–L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters

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Temperature Sensing RRAM Architecture for 3-D ICs

A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory

An Equation-Based Circuit Model and Its Generation Tool for 3-D IC Power Delivery Networks With an Emphasis on Coupling Effect

Metrology and Inspection Requirements for Successful Stacking of Integrated Circuits

Flow and rank correlation based detection against Distributed Reflection Denial of Service attack

Parasitic Back-Gate Effect in 3-D Fully Depleted Silicon on Insulator Integrated Circuits

Characterization of the Proximity Effect From Tungsten TSVs on 130-nm CMOS Devices in 3-D ICs

Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits

L1&#x2013;L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters

L1–L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters