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Message from the Symposium Chair

Publisher:
IEEE
Year
: 2014
DOI: 10.1109/PCCC.2014.7017093
URI: https://libsearch.um.ac.ir:443/fum/handle/fum/997852
Keyword(s): cache storage,graph theory,memory architecture,multiprocessing systems,real-time systems,WCET analysis approach,large-on-chip caches,multicore processors,nonuniform cache architecture,real-time systems,static NUCA cache topologies,uniform access time,wire delays,worst-case execution time,worst-case performance improvement,Benchmark testing,Delays,Equations,Mathematical model,Multicore processing,Program processors
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    Message from the Symposium Chair

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date accessioned2020-03-12T19:59:35Z
date available2020-03-12T19:59:35Z
date issued2014
identifier other6844983.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/997852
formatgeneral
languageEnglish
publisherIEEE
titleMessage from the Symposium Chair
typeConference Paper
contenttypeMetadata Only
identifier padid8117876
subject keywordscache storage
subject keywordsgraph theory
subject keywordsmemory architecture
subject keywordsmultiprocessing systems
subject keywordsreal-time systems
subject keywordsWCET analysis approach
subject keywordslarge-on-chip caches
subject keywordsmulticore processors
subject keywordsnonuniform cache architecture
subject keywordsreal-time systems
subject keywordsstatic NUCA cache topologies
subject keywordsuniform access time
subject keywordswire delays
subject keywordsworst-case execution time
subject keywordsworst-case performance improvement
subject keywordsBenchmark testing
subject keywordsDelays
subject keywordsEquations
subject keywordsMathematical model
subject keywordsMulticore processing
subject keywordsProgram processors
identifier doi10.1109/PCCC.2014.7017093
journal titleultiple-Valued Logic (ISMVL), 2014 IEEE 44th International Symposium on
filesize71773
citations0
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