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SMV methodology enhancements for high speed I/O links of SoCs

date accessioned2020-03-12T19:46:37Z
date available2020-03-12T19:46:37Z
date issued2014
identifier other6818767.pdf
identifier urihttps://libsearch.um.ac.ir:443/fum/handle/fum/989698?show=full
formatgeneral
languageEnglish
publisherIEEE
titleSMV methodology enhancements for high speed I/O links of SoCs
typeConference Paper
contenttypeMetadata Only
identifier padid8105960
subject keywordsArtificial neural networks
subject keywordsForecasting
subject keywordsGenetic algorithms
subject keywordsLoad forecasting
subject keywordsLoad modeling
subject keywordsPredictive models
subject keywordsTraining
subject keywordsFeed-forward neural network
subject keywordsgenetic algorithm
subject keywordspower System Planning
subject keywordsradial basis function neural network
subject keywordsshort-term load forecasting
identifier doi10.1109/AUPEC.2014.6966627
journal titleLSI Test Symposium (VTS), 2014 IEEE 32nd
filesize539848
citations0
contributor rawauthorViveros-Wacher, A. , Alejos, R. , Alvarez, L. , Diaz-Castro, I. , Marcial, B. , Motola-Acuna, G. , Vega-Ochoa, E.-A.


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